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MSPM0G1107: Base register locations, lack of clarity in documentation

Curtis Villamizar
Prodigy 10 points
Part Number: MSPM0G1107
Other Parts Discussed in Thread: MSPM0-SDK

Tool/software:

I need better documentation of base register locations.  I am looking at MSPM0 G-Series 80MHz Microcontrollers  Technical Reference Manual and the MSPM0G110x Mixed-Signal Microcontrollers datasheet.  Neither is clear about where the base register SYSCTL is or the offset to SYSCTL.IOMUX and SYSCTL.IOMUX.PINCM which is described in TRM as an offset of 4h (from where) and is described as a single entry (it seems obvious that it is an array indexed by PINCM num).  I've looked at TI open source from https://github.com/TexasInstruments/mspm0-sdk/tree/main and the base registers in mspm0-sdk/source/ti/devices/msp/m0p/mspm0g110x.h don't seem to agree with the TRM offsets.  The memory map in the TRM only provides a base of 0x4000.0000 for peripheral memory, but little else of use.

Is there some place where the base addresses of such things as peripheral memory base locations are accurately documented?  Besides RTFC with the open software and hope its right.

  • 0
    Prodigy 10 points

    The address of IOMUX is in Table 8-5. Peripherals Summary in the datasheet.  TRM cites PINCM as Pin Control Management Register in SECCFG region but has no relevant reference to SECCFG and data sheet has no mention of SECCFG.  All other mentions of SECCFG in TRM are to SYSCTL.SECCFG which has no relationship to IOMUX.SECCFG which has no mention.  Using both these documents and RTFC methodology I resolved this but would like to report this as a documentation bug.

  • 0 in reply to Curtis Villamizar
    TI__Expert 8395 points

    Hi,

    Thanks for your report about this problem. Refer to the source code of these registers is the most direct way to get register address.