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MCU-PLUS-SDK-AM263PX: MCU-PLUS-SDK-AM263PX

Part Number: MCU-PLUS-SDK-AM263PX

Tool/software:

I have imported IPC rpmsg echo R5FFS0_0 and IPC rpmsg echo R5FFS0_1  example project from the SDK 9.01.00.20 and disabled the shared memory with the R5FSS1_0  core and R5FSS1_1 core in both example projects ,build the project as a system but still i am getting an error.

  • Hello Rapeti,

    Can you download the latest version of the SDK (10.01.00.34) from the link below and confirm the issue still exists?

    MCU-PLUS-SDK-AM263PX Software development kit (SDK) | TI.com

    When you say: 

    disabled the shared memory with the R5FSS1_0  core and R5FSS1_1 core

    What steps were taken here?

    If you provide an index of 0 does the error go away?

    (unitptr_t)(&gIpcSharedMem[0]);

    Thanks and Regards,

    Zackary Fleenor

  • I have downloaded the latest version of the SDK (10.01.00.34), the issue still exists.

    Disabled the shared memory with the R5FSS1_0  core and R5FSS1_1 core means:

    I am using IPC for R5FSS0_0 and R5FSS0_1 so in Sys Config i have disabled the shared memory with the R5FSS1_0  core and R5FSS1_1 core. Attached the image.

    If you provide an index of 0 does the error go away?

    (unitptr_t)(&gIpcSharedMem[0]);

    Above statement is in derived Sys Config file ( ti_drivers_config.c) .

  • Hey Rapeti,

    A shared memory definition between R5FSS1_0 and R5FSS1_1 is required in order for the IPC example to build and execute as expected.

    What is the reasoning for disabling this from the default configuration?

    If you don't disable this shared memory, do you still experience the error?

    Best Regards,

    Zackary Fleenor

  • What is the reasoning for disabling this from the default configuration?

    I have followed as given in faq-mcu-sdk-build-error-expected-expression-rpmsgparams-vringtxtaseaddr.

     yes even if the shared memory is not disabled i am getting the same error: rpmsgParams.vringTxBaseAddr[CSL_CORE_ID_R5FSS0_0] = (unitptr_t)(&gIpcSharedMem[]); expected expression error for all subsystem cores (R5FSS0_0,R5FSS1_0,R5FSS1_1).

  • Hey Rapeti,

    Thank you for sharing this information. As mentioned by Nick S. on the previous thread you shared: When generating a project that uses multiple cores, you need to build the _system level project and not the specific core version of the project.

    Based on the CCS screenshot you shared earlier; you are building the "ipc_rpmsg_echo_am263px-lp_r5fss0-1_nortos" project. Instead, you should build the "ipc_rpmsg_echo_am263px-lp_system_freertos_nortos". The system project configuration will handle building the .out files for each r5fssX-Y core and combine them into a single multicore_elf file to load/debug.

    Best Regards,

    Zackary Fleenor

  • If i have imported a system project my issue got resolved but, if i have created 2 Core projects using two empty project which are dependent on each other then what is the procedure to make them as system project and to add IPC as communication between them.

  • Hey Rapeti,

    Apologies for the delayed response here.

    This is not the recommended way to create a multi-core project that will rely on IPC. Instead, the recommendation is to start with the system project definition and implement two empty projects with IPC.

    Details on implementing a new system project and utilizing the CCS System Settings view can be found on the link below:

    https://dev.ti.com/tirex/explore/node?node=A__ASnAOQq-ZZCy9h2t-TfIOQ__AM26X-ACADEMY__t0CaxbG__LATEST

    Please review this content and implement as defined. You can use the ipc_rpmsg_echo_am263px-lp_system_freertos_nortos as a guideline for how to implement IPC in the empty system project.

    Since your original issue has been resolved, please create a new e2e thread for further questions to help manage traceability.

    Thanks and Regards,

    Zackary Fleenor