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AM2634: Technical Reference Manual Clocking Section Typos

Andy MacGregor
Intellectual 257 points
Part Number: AM2634

Tool/software:

Hi, I've been reading the AM263x TRM revision H section 6.4 on Clocking. I've noticed the following inconsistencies. Please correct me if I have made the wrong assumptions:

Figure 6-22:  
Two different signals are labelled "DPL_CORE_HSDIV0_CLKOUT1". I assume the 192MHz instance should be labeled DPLL_PER_HSDIV0_CLKOUT1?
AM263 TRM RevH. Figure 6-22

6.4.7.2.4 MCSPI CLOCK:

The steps to cofingure this clock at 50MHz say to use CLKDIV = "3" and CLKSRCSEL = "4" (DPLL_CORE_HSDIV0_CLKOUT0). However Table 6-28 shows DPLL_CORE_HSDIV0_CLKOUT0 has 400MHz frequency, so I think these registers would set configure this clock to 400Mhz/4=100MHz. I asume that I should use to use CLKDIV = "3" and CLKSRCSEL = "2" (SYS_CLK 200MHz) to configure this clock to 50MHz?

6.4.7.2.10 CPTS Clock:

This section says "Update the CPTS GCM register with the value of 0x333 to select PLL_PER_CLKOUT1 as its source, MSS_RCM.CPTS_CLK_SRC_SEL.CLKSRCSEL = 0x333". However Table 6-31 shows that for CPTS, CLKSRCSEL=3 maps to DPLL_CORE_HSDIV0_CLKOUT1. I assume that the quoted sentence means to say "DPLL_CORE_HSDIV0_CLKOUT1 as its source" instead?

  • 0
    Intellectual 257 points

    I have one more.

    6.4.7.2.23 MSS_ELM CLOCK:

    This section says "Program ... SYS_CLK, MSS_RCM.MSS_LM_CLK_DIV_VAL.CLKDIV = 0x03". However in the Register Addendum (Rev E.), documentation for the CLKDIV field says "Data should be loaded as multibit" and that the default value is 0x333. The register name is missing an 'E' and I think I should write 0x333 to this register instead.

  • +1
    TI__Expert 5446 points

    Hello Andy,

    Apologies for the late response here. I've verified that all the inconsistencies pointed out are valid. I've raised an internal bug to fix these in the next revision. Thanks for bringing them to our attention.

    Andy MacGregor said:
    I assume the 192MHz instance should be labeled DPLL_PER_HSDIV0_CLKOUT1?

    Yes, that is right.

    Andy MacGregor said:
    I think these registers would set configure this clock to 400Mhz/4=100MHz. I asume that I should use to use CLKDIV = "3" and CLKSRCSEL = "2" (SYS_CLK 200MHz) to configure this clock to 50MHz?

    Yes, that can be done, or you could change the CLKDIV value to "7" in order to get 50MHz.

    Andy MacGregor said:
    I assume that the quoted sentence means to say "DPLL_CORE_HSDIV0_CLKOUT1 as its source" instead?

    Yes, that is correct.

    Andy MacGregor said:
    The register name is missing an 'E' and I think I should write 0x333 to this register instead.

    Yes, this is right.

    Regards,

    Sahana