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AM2434: Multicore Memory Map Layout with EIP core

Matej Liska
Prodigy 90 points
Part Number: AM2434


Tool/software:

Hello,

We are currently designing an application that operates on a multicore architecture utilizing the prebuilt QSPI Multipartition SBL. Our setup includes the EIP core running on R5F0_0, which has a memory size exceeding 256KB. The encrypted application resides in the R5F0_1 core. 

Based on the AM243X memory map documentation from https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_01_00_32/exports/docs/api_guide_am243x/MEMORY_MAP.html 
we are aware of the potential race conditions if the application running on R5F0_1 starts before the SBL on R5F0_0 has finished. (For example, EtherCAT example running on R5F0_0, uses all the banks except the ones reserved for SBL and DMSC, but we have also second application on core R5F0_1)

To ensure safe operation, we are looking for recommendations on the following:

Memory Management: What strategies can we implement to guarantee proper memory allocation and avoid race conditions during the initialization of the two cores?

SBL Modification: Are there specific changes we can make to the SBL or the prebuilt SBL to ensure smooth startup and flashing of both cores, considering one core will handle encrypted firmware?

Are memory regions of MSRAM fixed addresses by HW or SW? How it can be modified for our purposes?

Any insights or suggestions would be greatly appreciated! Thank you for your assistance.


Thank you.

BR,
Matej Liska.

  • 0
    TI__Genius 15505 points

    Hi Matej,

    I am looking into your queried, I will get back to you as soon as I have an update.

    Best Regards,

    Meet.

  • 0 in reply to Meet Thakar
    Prodigy 90 points

    Hi Meet,
    any updates on this topic?
    Thank you.

  • 0 in reply to Matej Liska
    TI__Genius 15505 points

    Hi Matej,

    Apologies for the delay.

    Matej Liska said:
    Memory Management: What strategies can we implement to guarantee proper memory allocation and avoid race conditions during the initialization of the two cores?

    You only have to worry about the race condition if you are loading any application (for core other than the R5F0-0) to the memory section reserved for SBL. In case you are not planning to load any application to the SBL reserved section then you do not have to worry about this. Please avoid loading the application on SBL reserved section if possible.

    Matej Liska said:
    SBL Modification: Are there specific changes we can make to the SBL or the prebuilt SBL to ensure smooth startup and flashing of both cores, considering one core will handle encrypted firmware?

    There is no need for any modification in the SBL, could you please elaborate what is meant by the encrypted firmware here?

    Matej Liska said:
    Are memory regions of MSRAM fixed addresses by HW or SW? How it can be modified for our purposes?

    These addresses are not fixed by the HW, as mentioned here: https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/10_01_00_32/exports/docs/api_guide_am243x/MEMORY_MAP.html If an application is using only one core, then it can use the banks reserved for other cores.This means that if you can use the memory sections in the Memory Map according to your requirement and the addresses are not fixed. You have to modify these addresses using the linker file of the example. For example, this is the address and length defined for R5F0-1's empty example:

    You can modify this to make it work for you.

    Best Regards,

    Meet.