MSPM0G1507: Unresolved DMA/ADC/SYSCTL names on CCS+MSPM0_SDK

Tool/software:

Hi,

I'm working with the MSPM0G1507 in the VQFN32 package and have written a simple example from scratch, based on the TI documentation.

I'm not using DriverLib because I couldn’t figure out how to configure a two-channel ADC setup for my use case with it, so I decided to implement everything manually.

However, I’m currently unable to compile the code. I'm using CCS 12.1.1.00008 (based on 20.1.1.8) and MSPM0 SDK 2.04. All include paths seem to be correctly set up, but identifiers like ADC, DMA, or SYSCTL are not recognized during compilation.

Could you please advise how to properly compile and run a bare-metal project like this?

Thanks in advance!

#include <ti/devices/msp/m0p/mspm0g150x.h>

#define ADC_LEN 640

uint16_t adc_buf_ch0[2][ADC_LEN];
uint16_t adc_buf_ch1[2][ADC_LEN];
volatile int sw = 0;

void DMA_IRQHandler(void)
{
    if (DMA->IRQSTATUS0 & DMA_IRQSTATUS0_DMA_CH0_MASK) {
        DMA->IRQSTATUS0 = DMA_IRQSTATUS0_DMA_CH0_MASK;
        sw ^= 1;
        DMA_CH0_CTL &= ~DMA_CH0_CTL_ENABLE_MASK;
        DMA_CH0_DSTADDR = (uint32_t)&adc_buf_ch0[sw][0];
        DMA_CH0_CTL |= DMA_CH0_CTL_ENABLE_MASK;
    }
    if (DMA->IRQSTATUS0 & DMA_IRQSTATUS0_DMA_CH1_MASK) {
        DMA->IRQSTATUS0 = DMA_IRQSTATUS0_DMA_CH1_MASK;
        DMA_CH1_CTL &= ~DMA_CH1_CTL_ENABLE_MASK;
        DMA_CH1_DSTADDR = (uint32_t)&adc_buf_ch1[sw][0];
        DMA_CH1_CTL |= DMA_CH1_CTL_ENABLE_MASK;
    }
}

void sysclk_on(void)
{
    SYSCTL->HFXTCR = SYSCTL_HFXTCR_ENABLE_MASK | SYSCTL_HFXTCR_HFXTFREQ_SEL_20MHZ;
    while (!(SYSCTL->STATUS & SYSCTL_STATUS_HFXT_GOOD_MASK));
    SYSCTL->CLKCFG = (SYSCTL->CLKCFG & ~SYSCTL_CLKCFG_HSCLK_SEL_MASK) |
                     (SYSCTL_CLKCFG_HSCLK_SEL_HFXT << SYSCTL_CLKCFG_HSCLK_SEL_OFS);
}

void sysclk_off(void)
{
    SYSCTL->HFXTCR &= ~SYSCTL_HFXTCR_ENABLE_MASK;
    SYSCTL->CLKCFG = (SYSCTL->CLKCFG & ~SYSCTL_CLKCFG_HSCLK_SEL_MASK) |
                     (SYSCTL_CLKCFG_HSCLK_SEL_HFCLK << SYSCTL_CLKCFG_HSCLK_SEL_OFS);
}

void adc_ini(void)
{
    ADC0->CTL0 = ADC12_CTL0_SAMPLING_MODE_SEQ | ADC12_CTL0_REPEAT_MODE;
    ADC0->STEPENABLE = 0x8F; // A0_0, A0_1, A0_2, A0_3, A0_7
    ADC0->FIFOCTL = ADC12_FIFOCTL_THRESHOLD_1;
    ADC0->DMACTL = ADC12_DMACTL_ENABLE_MASK;
    ADC0->CTL1 |= ADC12_CTL1_CONVERSION_ENABLE_MASK;
    ADC0->SWTRIG = ADC12_SWTRIG_START_MASK;

    ADC1->CTL0 = ADC12_CTL0_SAMPLING_MODE_SEQ | ADC12_CTL0_REPEAT_MODE;
    ADC1->STEPENABLE = 0x8F; // A1_0, A1_1, A1_2, A1_3, A1_7
    ADC1->FIFOCTL = ADC12_FIFOCTL_THRESHOLD_1;
    ADC1->DMACTL = ADC12_DMACTL_ENABLE_MASK;
    ADC1->CTL1 |= ADC12_CTL1_CONVERSION_ENABLE_MASK;
    ADC1->SWTRIG = ADC12_SWTRIG_START_MASK;

    DMA_CH0_SRCADDR = (uint32_t)&ADC0->FIFODATA;
    DMA_CH0_DSTADDR = (uint32_t)&adc_buf_ch0[sw][0];
    DMA_CH0_XFER_SIZE = ADC_LEN;
    DMA_CH0_CTL = DMA_CH0_CTL_DST_INC_MASK | DMA_CH0_CTL_SRC_FIXED_MASK | DMA_CH0_CTL_ENABLE_MASK;

    DMA_CH1_SRCADDR = (uint32_t)&ADC1->FIFODATA;
    DMA_CH1_DSTADDR = (uint32_t)&adc_buf_ch1[sw][0];
    DMA_CH1_XFER_SIZE = ADC_LEN;
    DMA_CH1_CTL = DMA_CH1_CTL_DST_INC_MASK | DMA_CH1_CTL_SRC_FIXED_MASK | DMA_CH1_CTL_ENABLE_MASK;

    NVIC_EnableIRQ(DMA_INT_IRQn);
}

void adc_off(void)
{
    DMA_CH0_CTL &= ~DMA_CH0_CTL_ENABLE_MASK;
    DMA_CH1_CTL &= ~DMA_CH1_CTL_ENABLE_MASK;

    ADC0->CTL1 &= ~ADC12_CTL1_CONVERSION_ENABLE_MASK;
    ADC1->CTL1 &= ~ADC12_CTL1_CONVERSION_ENABLE_MASK;

    ADC0->CTL0 = 0;
    ADC1->CTL0 = 0;
}


int main()
{ SYSCFG_DL_init();
  adc_ini();
  while(1)
  { if(sw) /* do some work */; else /* do some work*/;
  }
}