TMS570LC4357: FCS calculated in microcontroller at hardware level and Ethernet PHY function in microcontroller reject with the incorrect FCS.

To answer these questions, I have referred to the device TRM: https://www.ti.com/lit/pdf/spnu563 

Nagabhushanabhat K said:

a) Frame Check Sequence (FCS) calculation and verification in the MAC (Media Access Control) layer of the TMS570LC4357 is handled at the hardware level.

Yes, it is handled in hardware.

Page 1811: A cyclic redundancy check (CRC) is used by the transmit and receive algorithms to generate a CRC value for the FCS field. The frame check sequence covers the 60 to 1514 bytes of the packet data.

Nagabhushanabhat K said:

b) Hardware MAC:

The TMS570LC4357 includes a hardware MAC module, which is responsible for managing the physical layer of the Ethernet communication.

Yes it is handled in hardware

Page 1804: 

The EMAC/MDIO has the following features: • Synchronous 10/100 Mbps operation. • Standard Media Independent Interface (MII) and/or Reduced Media Independent Interface (RMII) to physical layer device (PHY). • EMAC acts as DMA master to either internal or external device memory space. • Eight receive channels with VLAN tag discrimination for receive quality-of-service (QOS) support. • Eight transmit channels with round-robin or fixed priority for transmit quality-of-service (QOS) support. • Ether-Stats and 802.3-Stats statistics gathering. • Transmit CRC generation selectable on a per channel basis. • Broadcast frames selection for reception on a single channel. • Multicast frames selection for reception on a single channel. • Promiscuous receive mode frames selection for reception on a single channel (all frames, all good frames, short frames, error frames). • Hardware flow control. • 8k-byte local EMAC descriptor memory that allows the peripheral to operate on descriptors without affecting the CPU. The descriptor memory holds enough information to transfer up to 512 Ethernet packets without CPU intervention. (This memory is also known as CPPI RAM.) • Programmable interrupt logic permits the software driver to restrict the generation of back-to-back interrupts, which allows more work to be performed in a single call to the interrupt service routine.

Nagabhushanabhat K said:

c) FCS Calculation:

The MAC hardware automatically calculates the FCS (also known as the Cyclic Redundancy Check or CRC) for transmitted frames and verifies the FCS for received frames. 

Yes, it is calculated on TX and verified on RX

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