TMS570LS3137: MibSPI5 on the 144-pin PGE package has only 1x chip-select (CS0)

Hi Chuck,

Chuck Wong said:

According to the device datasheet SPNS162C, the MibSPI5 peripheral in this package provides only 1x chip-select (CS0) to the outside, while the MCU has internally up to 4 CS (_nCS[3:0] for the BGA package, for example).

You are correct for 144-pin package there is only one chip select line available on MibSPI5.

Chuck Wong said:

• Use the MibSPI1 CS0 to connect to one SPI device #1
• Tape an inverter to the CS0 line and connect its output to SPI device #2
• To exchange with device #1, pull down CS0 as normally do
• To exchange with device #2, raise CS0 by selecting any other CS (3, 2, or 1)
• Does the MCU allow this even when other CS signals are not routed to the outside?

I don't think this is a good idea because we can't disable both the devices if needed. At any given instance of time one of the device SPI chip-select will be active right?

This might create issues, there won't be any ideal condition where both the devices chip select can be OFF. At any instance of time at least one slave will expect clock and data.

Instead of this method you can use another GPIO as chip-select for another slave. I mean connect CS line of MibSPI5 to slave-1 and GPIO to the other slave-2. You already knew how to communicate with slave-1 which is operating with CS line right, now if you want to communicate with slave-2 then you can simply disable the CS functionality of the slave-1 and enable the slave-2 CS using GPIO. If you write low on the GPIO it will enable the chip-select for slave-2 and then you can proceed with your communication.

Again, if you want to communicate with slave-1 then you can disable slave-2 CS by simply writing logic high on GPIO and then you can enable CS functionality for mibspi. Actually many customers will use this method only when they lack the chip-selects.

--
Thanks & regards,
Jagadish.

Hi Jagadish,

Thank you for your prompt reply. The method that you proposed above was the first method that came to my mind. However, we might have to start the communication directly via DMA transfers, from the MCU RAM to the MibSPI5 TXRAM, so it won't be practical to enable a GPIO before the transfers, unless there are tweaks that we can do to overcome that ...

About the "CS0 inverter" method in my question, since the SPI5 will be dedicated to 2 slave devices, what could be dangerous if one being always listening to the SPI bus, and if there is no data on the line? Potential noise issues?

Regards,

Chuck.