MSPM0G3107: Register access time

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Part Number: MSPM0G3107

Tool/software:

Hello,

I am testing MSPM0G350x.

How many clocks cost to access each register from CPU? ALL register is 1 CPU clocks?

Or Is it depends on peripheral side bus clock? (such as IOMUX register = ULPCLK, UART3 = MCLK)

Thanks,

+1 Sal Ye 9 months ago

Hi GR,

See below thread for your reference, there also has the similar question on the CPU cycles during access peripheral register:

B.R.

Sal

0 GR 9 months ago in reply to Sal Ye

Genius 3186 points

Hi Sal,

Thanks for your information.

I understand as below:

For GPIO, there is no latency, and 1 cycles.

For PD1 (MCLK), there is 1 additional cycles latency, and is total 3 cycles.

For PD0 (ULPCLK), there is 3 additional cycles latency, and is total 5 cycles.

Best regards,

Arm-based microcontrollers forum