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AM263P4: Suggestion for implementing ADC oversampling with more than 4 channels

Huey Duong
Intellectual 290 points
Part Number: AM263P4

Tool/software:

Hi, I am currently looking at implementing the ADC design for our project.

In summary ADC1-4 will be used.  Each ADC may have 4-6 channels to convert.  We want to do oversampling: converting all channels 4 times, then take results and post process the data to calculate the averages of all conversions.

Other information:

  • PWMs running @ 40Khz, ADC conversion and control code running at 20khz
  • PWM0 will generate ADCSOCA that triggers all ADC conversions
  • At the end of oversampling all ADCs, the results are processed to calculate averages and then the control code is run.  Currently ADC1 EOC5 triggers an interrupt XBAR

There seems to be a couple of solutions, but neither is ideal.  Can TI help provide a best approach here or suggest a different implementations.

### Implementation #1 (PPB & Repeaters):

  • Set up all SOCs to trigger using repeater set to x4
  • Set up PPB to sum and find min/max
  • Set up PPC OSINT to generate ISR and run Control code

Challenges with this method:

  1. There are only 4 PPB per ADC.  Some ADCs have > 4 SOCs.  Is this method even possible given we need > 4 PPB per ADC?
  2. Still need to keep track of remaining ADC results so that averaging math can be done in SW.

### Implementation #2 (continuous DMA):

  • Create an ADC results memory buffer.
  • Set up last EOC to generate ADCINT1
  • Set up all SOCs for continuous conversion
  • Set up DMA to copy all ADCRESULT regs from SOC0-SOCx to memory buffer on last EOC.
  • Set up DMA generate interrupt when buffer is filled.  (ie. 4xSOC RESULTS)  which then runs processes buffer for average and runs control code

Challenges with this method:

  • Much more involved.
  • How does ADC stop converting after buffer is full?
  • Can DMA copy all SOC Results to an offset that automatically increments?  (Not much DMA experience here)
  • Is the DMA latency comparable to a simple ISR that copies the result registers?
  • Due to errata i2355, how many DMAs do we need?  4 ADC x 2 = 8?

Any other suggestions? I'm hoping to get some suggestions from experienced AM263 developers here.

Thanks for the support.

  • 0
    TI__Expert 4230 points

    Hi Huey

    Implementation #1 doesn't seem like a good option as this method is not feasible if any ADC requires > 4 channels due to the PPB limit. Even with <= 4 channels, efficiently gathering all results for averaging without losing data before the OSINT fires is problematic without resorting to frequent EOC interrupts, which undermines the benefit of the repeater/OSINT.

    for Implementation #2

    Huey Duong said:
    Due to errata i2355, how many DMAs do we need?  4 ADC x 2 = 8?

    The errata 2355 is not applicable to am263p. use alternativeTrigger for DMA from the IP.

    Huey Duong said:
    How does ADC stop converting after buffer is full?

    The ADC doesn't need to stop. It converts continuously based on the PWM trigger. The DMA ensures you capture coherent sets of 4 conversions into your buffer for processing.

    Huey Duong said:
    Is the DMA latency comparable to a simple ISR that copies the result registers?

    Generally much lower and more predictable than ISR overhead for reading multiple registers. Ideal for this kind of data throughput.

    You can try to emulate the following approach:

    1. PWM0 SOCA triggers SOC0-SOCx on all ADCs.

    2. ADCxINT1 configured to trigger after the last SOC of that ADC finishes conversion

    3. DMA channels (one per ADC) triggered by the corresponding ADCxINT1 event.

    4. DMA transfers results directly from ADCRESULT registers to RAM with minimal CPU intervention after each conversion pass for an ADC is complete (signaled by ADCxINT1).

    5. Managing 4 Passes: A ping-pong buffer approach combined with a DMA completion interrupt is robust:

    • Allocate two buffers (A and B), each large enough for 4 * TOTAL_CHANNELS results.
    • DMA writes to the currently active buffer (e.g., A).
    • Use the DMA Transfer Complete (TC) interrupt from one of the DMA channels (e.g., the one for ADC4) as a signal that one pass of results for all ADCs has been transferred (assuming ADC4's last SOC is the last one overall to finish, or simply use it as a convenient sync point).
    • In the DMA TC ISR, increment a software counter.
    • When the counter reaches 4:
    • Signal the main application that a full block is ready for processing (pass the pointer to buffer A)
    • Switch the DMA destination pointers for all 4 channels to buffer B.
    • Reset the counter.
    • The application processes buffer A while DMA fills buffer B.
    • Next time the counter reaches 4 in the ISR, signal the app with buffer B, and switch DMA back to buffer A.

    Let me know if this helps, I'll try to replicate the setup n my own end for the meanwhile!

    Regards,
    Akshit