AM2612: custom flash adaption

/*
 *  Copyright (C) 2021-24 Texas Instruments Incorporated
 *
 *  Redistribution and use in source and binary forms, with or without
 *  modification, are permitted provided that the following conditions
 *  are met:
 *
 *    Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 *
 *    Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the
 *    distribution.
 *
 *    Neither the name of Texas Instruments Incorporated nor the names of
 *    its contributors may be used to endorse or promote products derived
 *    from this software without specific prior written permission.
 *
 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <kernel/dpl/DebugP.h>
#include "ti_drivers_open_close.h"
#include "ti_board_open_close.h"
#include <drivers/bootloader/bootloader_uniflash/bootloader_uniflash.h>
#include <drivers/ospi/v0/lld/ospi_lld.h>
#include <drivers/hw_include/cslr.h>

#define FILE_MAX_SIZE   (0x140000) /* This has to match the size of MSRAM_1 section in linker.cmd */
uint8_t gFileBuf[FILE_MAX_SIZE] __attribute__((aligned(128), section(".bss.filebuf"))); 

#define VERIFY_BUF_MAX_SIZE (32*1024)
uint8_t gVerifyBuf[VERIFY_BUF_MAX_SIZE] __attribute__((aligned(128), section(".bss")));

#define INPUT_STR_MAX_LEN   (16u)
static char inputStr[INPUT_STR_MAX_LEN];

#define FILE_NAME_MAX_LEN   (384u)

/* Some common NOR XSPI flash commands */
#define OSPI_NOR_CMD_RDID           (0x9FU)
#define OSPI_NOR_CMD_RSTEN          (0x66U)
#define OSPI_NOR_CMD_RST            (0x99U)
#define OSPI_NOR_CMD_WREN           (0x06U)
#define OSPI_NOR_CMD_RDSR           (0x05U)
#define OSPI_NOR_CMD_RDSFDP         (0x5AU)

#define OSPI_NOR_SR_WIP             (1U << 0U)

#define OSPI_NOR_SFDP_DC            (8U)

#define OSPI_NOR_WRR_WRITE_TIMEOUT  (600U*1000U)

static uint8_t gNorRdCmd = 0x03;
static uint8_t gNorWrCmd = 0x02;
static uint8_t gNorErCmd = 0xD8;

static char filename[FILE_NAME_MAX_LEN];

void flashFixUpOspiBoot(OSPI_Handle oHandle);
void gpio_flash_reset(void);
void custom_protocol_setting(void);
int32_t OSPI_lld_norFlashInit1s1s4s(OSPILLD_Handle hOspi);

char gMainMenu[] = {
    " \r\n"
    " \r\n"
    " ==================\r\n"
    " JTAG Uniflash Menu\r\n"
    " ==================\r\n"
    " \r\n"
    " 1: Erase Complete Flash\r\n"
    " 2: Write File to Flash and Verify\r\n"
    " 3: Verify file in Flash\r\n"
    " \r\n"
    " x: Exit\r\n"
    " \r\n"
    " Enter Choice: "
};

int32_t sbl_jtag_uniflash_load_file(char optype)
{
    int32_t status = SystemP_SUCCESS;
    uint32_t offset;
    uint32_t fileSize;
    uint32_t eraseBlkSize;
    uint32_t flashSize;
    FILE *fp;

    DebugP_log("\r\n");
    DebugP_log(" Enter file name along with path to write or verify : ");
    gets(filename);
    fp = fopen(filename, "rb");
    if(fp == NULL)
    {   /* if file not present then exit */
        DebugP_log(" [FLASH WRITER] Unable to open file %s !!!\r\n", filename);
        status = SystemP_FAILURE;
    }
    if(status==SystemP_SUCCESS)
    {   /* if file size > buffer size then exit, we will load the file in one shot so
         * so file size has to be < buffer size
         */
        fseek(fp, 0, SEEK_END); 
        fileSize = ftell(fp);
        fseek(fp, 0, SEEK_SET);
        fclose(fp);

        if(fileSize > FILE_MAX_SIZE)
        {
            DebugP_log(" [FLASH WRITER] File is too large to flash !!!\r\n");
            status = SystemP_FAILURE;
        }
    }
    if(status==SystemP_SUCCESS)
    {
        DebugP_log(" Enter flash offset (in hex format) : ");
        gets(inputStr);
        offset = strtol(inputStr, NULL, INPUT_STR_MAX_LEN);
    }
    if(status==SystemP_SUCCESS)
    {
        Flash_Attrs *flashAttrs;
        flashAttrs = Flash_getAttrs(CONFIG_FLASH0);
        if(flashAttrs == NULL)
        {
            status=SystemP_FAILURE; 
            DebugP_log(" [FLASH WRITER] Flash attributes are invalid !!!\r\n");
        }    
        else
        {
            eraseBlkSize = flashAttrs->blockSize;
            flashSize = flashAttrs->flashSize;

            if( (offset % eraseBlkSize) != 0)
            {
                DebugP_log(" [FLASH WRITER] Flash offset MUST be multiple of erase block size of 0x%08x !!!\r\n",
                    eraseBlkSize
                    );
                status = SystemP_FAILURE;
            }
            if( (offset+fileSize) > flashSize)
            {
                DebugP_log(" [FLASH WRITER] Flash offset + file size MUST be <= flash size of %d bytes !!!\r\n",
                    flashSize
                    );
                status = SystemP_FAILURE;
            }
        }
    }
    if(status==SystemP_SUCCESS)
    {
        /* load file via CCS scripting console, since otherwise it is very slow */
        { /* convert \\ to / */
            uint32_t i = 0;
            while(filename[i]!=0)
            {
                if(filename[i]=='\\')
                    filename[i]='/';
                i++;
            }
        }
        /* clear buffer to reset stale data if any */
        memset(gFileBuf, 0, FILE_MAX_SIZE);

        /* Construct the header depending on the option provided so that Bootloader_uniflashProcessCommands can be used */
        Bootloader_UniflashFileHeader uniflashHeader;

        uniflashHeader.magicNumber = BOOTLOADER_UNIFLASH_FILE_HEADER_MAGIC_NUMBER;
        uniflashHeader.offset = offset;
        uniflashHeader.actualFileSize = fileSize;

        if(optype == '2')
        {
            /* Operation is FLASH */
            uniflashHeader.operationTypeAndFlags = BOOTLOADER_UNIFLASH_OPTYPE_FLASH;
        }
        else if(optype == '3')
        {
            /* Operation is FLASH VERIFY */
            uniflashHeader.operationTypeAndFlags = BOOTLOADER_UNIFLASH_OPTYPE_FLASH_VERIFY;
        }
        else
        {
            /* Operation is invalid */
            uniflashHeader.operationTypeAndFlags = 0U;
        }

        if(uniflashHeader.operationTypeAndFlags == 0U)
        {
            status = SystemP_FAILURE;
        }
        else
        {
            /* Load the image after the header */
            memcpy(gFileBuf, (void *)&uniflashHeader, sizeof(uniflashHeader));

            DebugP_log(" Enter below command in CCS scripting console to load the file data to memory.\r\n");
            DebugP_log(" AFTER the file load is done, enter '1' to continue ...\r\n");
            DebugP_log("\r\n");
            DebugP_log(" loadRaw(0x%08x, 0, \"%s\", 32, false);",
                gFileBuf + sizeof(uniflashHeader), filename);
            DebugP_log("\r\n");

            /* wait for user input */
            do {
                gets(inputStr);
            } while(inputStr[0]!='1');

            /* Process the buffer */
            Bootloader_UniflashConfig uniflashConfig;
            Bootloader_UniflashResponseHeader respHeader;

            uniflashConfig.flashIndex = CONFIG_FLASH0;
            uniflashConfig.buf = gFileBuf;
            uniflashConfig.bufSize = 0; /* Actual filesize is part of the header */
            uniflashConfig.verifyBuf = gVerifyBuf;
            uniflashConfig.verifyBufSize = VERIFY_BUF_MAX_SIZE;

            /* Process the flash commands and return a response */
            Bootloader_uniflashProcessFlashCommands(&uniflashConfig, &respHeader);

            if(respHeader.statusCode == BOOTLOADER_UNIFLASH_STATUSCODE_SUCCESS)
            {
                if(optype == '2')
                {
                    DebugP_log(" [FLASH WRITER] Flashing success!!... \r\n");
                }
                else if(optype == '3')
                {
                    DebugP_log(" [FLASH WRITER] Verifying success!!... \r\n");
                }
                status = SystemP_SUCCESS;
            }
            else
            {
                status = SystemP_FAILURE;
            }
        }
    }

    return status;
}

void sbl_jtag_uniflash_erase_all(void)
{
    int32_t status;
    DebugP_log(" [FLASH WRITER] Erasing complete flash ... \r\n");
    DebugP_log(" [FLASH WRITER] This can take few minutes, so please wait ... \r\n");

    status = Flash_eraseBlk(gFlashHandle[CONFIG_FLASH0], (uint32_t)-1);

    if(status!=SystemP_SUCCESS)
    {
        DebugP_log(" [FLASH WRITER] Erasing complete flash ... ERROR !!!\r\n");
    }
    else
    {
        DebugP_log(" [FLASH WRITER] Erasing complete flash ... SUCCESS !!!\r\n");
    }
}

int main(void)
{
    int32_t status = SystemP_SUCCESS;
    char ch[16];

    System_init();
    /* Open OSPI Driver, among others */
    Drivers_open();

	/* ROM doesn't reset the OSPI flash. This can make the flash initialization
    troublesome because sequences are very different in Octal DDR mode. So for a
    moment switch OSPI controller to 8D mode and do a flash reset. */
    flashFixUpOspiBoot(gOspiHandle[CONFIG_OSPI0]);

    /* Open Flash drivers with OSPI instance as input */
    status = Board_driversOpen();

    custom_protocol_setting();

//    OSPI_lld_norFlashInit1s1s4s(gOspiConfig[CONFIG_OSPI0].object->ospilldHandle);
    if(status!=SystemP_SUCCESS)
    {
        DebugP_log(" [FLASH WRITER] Unable to open FLASH !!!\r\n");
    }

    if(status==SystemP_SUCCESS)
    {
        while(1)
        {
            DebugP_log(gMainMenu);

            gets(ch);

            switch(ch[0])
            {
                case '1':
                    sbl_jtag_uniflash_erase_all();
                    break;
                case '2':
                case '3':
                    status = sbl_jtag_uniflash_load_file(ch[0]);
                    if(status != SystemP_SUCCESS)
                    {
                        if (ch[0] == '2')
                        {
                            DebugP_log(" [FLASH WRITER] Write Failed !!!\r\n");
                        }
                        else if (ch[0] == '3')
                        {
                            DebugP_log(" [FLASH WRITER] Verify Failed !!!\r\n");
                        }
                    }
                    break;
                case 'x':
                break;
                default:
                    DebugP_log(" Enter valid option !!!\r\n");
                break;                
            }
            if(ch[0] == 'x')
                break;
        }
    }
    if(status != SystemP_SUCCESS)
    {
        DebugP_log("Some tests have failed!!\r\n");
    }
    else
    {
        DebugP_log("\r\n");
        DebugP_log(" [FLASH WRITER] Application exited !!!\r\n");
        DebugP_log("All tests have passed!!\r\n");
    }
    
    gpio_flash_reset();

    Board_driversClose();
    Drivers_close();
}

void flashFixUpOspiBoot(OSPI_Handle oHandle)
{
    gpio_flash_reset();
    OSPI_enableSDR(oHandle);
    OSPI_clearDualOpCodeMode(oHandle);
    OSPI_setProtocol(oHandle, OSPI_NOR_PROTOCOL(1,1,1,0));
}

void custom_protocol_setting(void)
{
    uint32_t cmd,data,addr;

    cmd = 0x00;     //<< 1s
    addr = 0x00;    //<< 1s
    data = 0x02;    //<< 4s

    uint32_t * ospiBaseAddress = (uint32_t *)(0x53808000U);

    uint32_t * readConfigAddress = ospiBaseAddress + 1U;
    uint32_t * writeConfigAddress = ospiBaseAddress + 2U;

    /* Transfer lines for Read */
    /* Set transfer lines for sending command */
    CSL_REG32_FINS(readConfigAddress, OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD, cmd);
    /* Set transfer lines for sending address */
    CSL_REG32_FINS(readConfigAddress, OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD, addr);
    /* Set transfer lines for sending data */
    CSL_REG32_FINS(readConfigAddress, OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD, data);

    /* Transfer lines for Write */
    /* Set transfer lines for sending address */
    CSL_REG32_FINS(writeConfigAddress, OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD, addr);
    /* Set transfer lines for sending data */
    CSL_REG32_FINS(writeConfigAddress, OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD, data);

}

int32_t OSPI_lld_norFlashInit1s1s4s(OSPILLD_Handle hOspi)
{
    int32_t status = OSPI_SYSTEM_SUCCESS;
    uint32_t regVal = 0U;
    uint8_t cmd;

    /* Check if the handle is NULL */
    if (NULL != hOspi)
    {
        const CSL_ospi_flash_cfgRegs *pReg = (const CSL_ospi_flash_cfgRegs *)(hOspi->baseAddr);

        /* Reset the Flash */
        cmd = OSPI_NOR_CMD_RSTEN;
        OSPI_norFlashCmdWrite(hOspi, cmd, 0xFFFFFFFF, NULL, 0);

        cmd = OSPI_NOR_CMD_RST;
        OSPI_norFlashCmdWrite(hOspi, cmd, 0xFFFFFFFF, NULL, 0);

        /* Wait for a while */
        uint32_t waitMicro = 500U * 1000U;
        hOspi->Clock_usleep(waitMicro);

        /* Set lowest bus clock */
        CSL_REG32_FINS(&pReg->CONFIG_REG,
                       OSPI_FLASH_CFG_CONFIG_REG_MSTR_BAUD_DIV_FLD,
                       0xF);

        /* SDR will be enabled in flash by default, set OSPI controller to 1S-1S-4S mode */

        /* Note:
           For the following fields:
           - Instruction type: remains 0 for 1s.
           - Address transfer type for standard SPI modes: 0 for 1s.
           - Data transfer type for extended mode: should be set to 2 for Quad (i.e. 4s).
        */

        /* Set number of address bytes as 3 to support legacy flash devices as well
            (00 = 1 addr byte, 01 = 2 addr bytes, 10 = 3, 11 = 4) */
        CSL_REG32_FINS(&pReg->DEV_SIZE_CONFIG_REG,
                       OSPI_FLASH_CFG_DEV_SIZE_CONFIG_REG_NUM_ADDR_BYTES_FLD,
                       0x02);

        /* Configure the Device Read Instruction Configuration Register */
        regVal = CSL_REG32_RD(&pReg->DEV_INSTR_RD_CONFIG_REG);

        /* Clear the bits for instruction type, non-XIP opcode, address and data transfer types, DDR enable, and dummy cycles */
        regVal &= ~(CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_MASK              |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_MASK       |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD_MASK                  |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_MASK);

        /* For 1s instruction & address, use 0.
           For 4s data, use 2. */
        regVal |= ((uint32_t)gNorRdCmd << CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_RD_OPCODE_NON_XIP_FLD_SHIFT) |
                  (2U << CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_SHIFT) |
                  (0U << CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_SHIFT) |
                  (0U << CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_INSTR_TYPE_FLD_SHIFT)          |
                  (0U << CSL_OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DUMMY_RD_CLK_CYCLES_FLD_SHIFT);

        CSL_REG32_WR(&pReg->DEV_INSTR_RD_CONFIG_REG, regVal);

        /* Configure the Device Write Instruction Configuration Register */
        regVal = CSL_REG32_RD(&pReg->DEV_INSTR_WR_CONFIG_REG);
        regVal &= ~(CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_MASK               |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_MASK |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_MASK |
                    CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DUMMY_WR_CLK_CYCLES_FLD_MASK);

        regVal |= ((uint32_t)gNorWrCmd << CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_WR_OPCODE_FLD_SHIFT) |
                  (0U << CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_ADDR_XFER_TYPE_STD_MODE_FLD_SHIFT) |
                  (2U << CSL_OSPI_FLASH_CFG_DEV_INSTR_WR_CONFIG_REG_DATA_XFER_TYPE_EXT_MODE_FLD_SHIFT);
        CSL_REG32_WR(&pReg->DEV_INSTR_WR_CONFIG_REG, regVal);

        /* Set read capture delay */
        status += OSPI_lld_setRdDataCaptureDelay(hOspi, 0);
    }
    else
    {
        status = OSPI_SYSTEM_FAILURE;
    }

    return status;
}