TMS570LC4357: MibSPI Parallel Mode Communication Issue on – Slave to Master Data Corruption

Tool/software:

Hi TI Team,

I am working with two TMS570LC4357 LaunchPads configured for MibSPI communication in parallel mode, using the following setup:

• Data Lines: 4 (Parallel Mode)

• Clock Speed: 18.75 MHz

• Transfer Group Size: 128

• Chip Select: 0

• ENA Pin: Not used

Master to Slave Communication (Working)

On the master side, I fill 128 buffers in the Tx RAM and trigger TG0. The slave receives the data successfully in its Rx RAM, and I’m able to copy it to a local buffer without any corruption.

Slave to Master Communication (Issue)

I am now attempting to transmit data from Slave to Master. To initiate the transfer, I send dummy data from the master (as expected in SPI full-duplex mode), while the slave sets its Tx RAM with valid data and triggers TG0. However, in this case, the data received by the master is getting corrupted.

I suspect I might be missing a step or misordering the sequence. Below is a simplified version of the relevant code:

Master:

mibspiSetData(mibspiREG5, 0ul, dummydata);      // Fill dummy data
mibspiTransfer(mibspiREG5, 0ul);                // Trigger TG0

while (1)
{
    mibspiGetData(mibspiREG5, 0ul, RecvBuf);    // Read received data

    if (RecvBuf[0] == 0xAAA1)                    // Example sync word
    {
        break;
    }
}

mibspiTransfer(mibspiREG5, 0);                  // Initially trigger TG0

while (1)
{
    mibspiGetData(mibspiREG5, 0, dummydata);    // Read dummy data from master

    if (dummydata[0] == 0xA5A5)                 // Sync condition
    {
        mibspiSetData(mibspiREG5, 0, source);   // Fill slave Tx RAM with data
        mibspiTransfer(mibspiREG5, 0);          // Re-trigger TG0
    }
}

Questions:

1. Is the sequence correct for slave-initiated transmission in this setup?

2. Should the slave trigger TG0 before or after receiving the dummy data?

3. Is there any specific timing requirement or synchronization mechanism required for correct slave-to-master data reception in parallel mode?

Thanks & Regards,
Naveen R