AM2434: EtherCAT connection problem with AM2434 and DP83822

Hi Christian,

Christian Br said:

2) Why ist the device not found, if fast link detection is enabled? This is a feature, which we want to support.

• For Enhanced Link/Fast Link Detection to work, make sure you have connected PRx_MII0_RXLINK and PRx_MII1_RXLINK and LEDs are configured correctly. LED configuration has to be a stable LINK (LED_SPEED or LED_LINK (without activity blink).
• Additionally for Fast Link Detection, make sure MDIO_USER_PHY_SEL_REG_j (offset 0x84 and 0x8C) bit7 are configured for MLINK (and keeping bit6 set).
• Refer to tiesc_ethphyInit() in tiescsoc.c (enhancedlink_enable = 1) for the above two configurations (I'm referring to a different EtherCAT implementation in the SDK but the initialization is identical).

Christian Br said:

1) Can you see a reason, why we cannot find our device on the second port?

• How are you configuring the EtherCAT IN and OUT port PHY Addresses? Is it based on the status of the MDIO_LINK_REG? So if you see the bit getting set/reset when you connect the in/out port to an active network using Ethernet cable, then you should configure that particular bit address as the PHY Address of the corresponding port.
• Additionally, when Fast Link Detection is disabled, make sure MDIO Manual Mode Link Status Update option is set to PHY Polling Based. 
  • 
• How is the behavior of MDIO_LINK_REG when the second port is connected? Are the bit corresponding to the PHY port getting set when the port is connected to an active network?

Christian Br said:

I also checked the EtherCAT status registers at offset 0x30090000 (device is connected in both cases, but without communication to TwinCAT):

• Can you monitor 0x30090E00 and 0x30090E04 to make sure RX Frame counter is getting incremented so that we can confirm frames are being received by the TI ESC (Firmware). Details of the register can be found at TI EtherCAT SubDevice Controller Register List.

Christian Br said:

I also tried both PHYPOLINVERT settings. MDIO__REGS_LINK_REG is set to 1, as i connect the device, so it should be High active.

• Yes this configuration is correct. The polarity should be ACTIVE_HIGH.

 Regards,
Aaron

Hi Aaron, 
just curious. How do you come to this address 0x0x30090000? 
Best,
Jinlong

Hi Aaron,

thanks a lot for the quick response and the advice.

I was now able to connect with TwinCAT wtih enabled Fast Link Detection. The problem was that LED_0 was configured as Low Active before (default setting). By setting it to High Active, i could find my device in TwinCAT, if connected to port 1. So problem 2) is solved.

In order not to get confused with 0´s and 1´s, we changed our PHY addresses to 0 and 9 now. I am able to to find the device in TwinCAT, if I connect to the PHY with address 0 (defined as IN). My settings are now as follows:

Hi

Christian Br said:

Do you have any further idea, what could cause this problem for the second port?

• Looks like there's some configuration missing for the MDIO with respect to the second PHY.
• Have you configured MDIO_USER_PHY_SEL_REG_j (0x300B2484 and 0x300B248C) correctly? 0x300B2484 should have value 0x000000C0 and 0x300B248C should have value 0x000000C9 in your case.
  • 
• For clarity, 0x300B2484 corresponds to first PHY and 0x300B248C corresponds to second PHY.

Regards,
Aaron

Hi Aaron,

this seems to be correct:

Any other ideas, what could cause the issue?

Best regards
Christian

I just did another test: If i connect a second board to the outport of my device (daisy chain), i can find both devices. So it doesn´t look like there is something wrong with the second port in general...

Hi Christian,

Looks like some configuration mismatch for the second port. Can you share the ICSS Memory dump during this scenario of scanning second port? Will check if there is any mismatch in the MII config registers or MDIO registers. Please share the complete memory dump.

Regards,
Aaron

Hi Aaron,

I paused the application while scanning in TwinCAT and exported all ICSSG1 registers (starting at Offset 0x30080000) to the attached file. Hope the format is okay like that (Filetype is TI Data). Please let me know if you need any further information.

Thanks again for your support!

Best regards
Christian

TI_ICSSG1Registers_Port2Connected.dat

Hi Christian, 

Thank you for sharing the dump. i will analyze this and get back to you.

Regards,
Aaron

Hi Aaron,

have you already been able to check the register content?

Best regards
Christian

Hi Christian,

Looks like the MDIO link status is not getting reflected in the EtherCAT firmware which configures the MII_RT Registers. There seems to be a mismatch in the MII_RT_RXCFG0 (0x300B2000) and MII_RT_RXCFG1 (0x300B2004) Registers which is configured using DL Status Register (0x0110):

The expectation here is that, when only second port is connected, bit3 of MII_RT_RXCFG0 should be set and bit3 of MII_RT_RXCFG1 should be 0:

0x300B2000 : 0x00000049
0x300B2004 : 0x00000051

In your case, the firmware is configuring the above registers for Port0 Closed, Port1 Closed scenario.

Couple of things to check on:

1. Are you able to scan for second port after disabling EnhancedLink/RXLINK?
2. When EnhancedLink is enabled, have you configured the polarity correctly? That is, when the cable is connected, if the MDIO link status bit is becoming 0, the polarity should be ACTIVE_HIGH. In this case, can you try the following configuration:

#define ECAT_PHYPOLINVERT_IN                (false)
#define ECAT_PHYPOLINVERT_OUT               (false)

Regards,
Aaron

Hi Aaron,

thanks for the information - very interesting!

Regarding you questions:

1. If I disable EnhacedLink detection (by setting ECAT_PHYUSERXLINK_IN/OUT to false), I can find the device on the second port. In this case, the mentioned registers are configured as described by you for the correct case.
2. In my opinion, the polarity should be correct. If I connect no port, register 0x3000B240C is 0x00000000. As I connect port 0, it is 0x00000001. For port 1 (phy address 9) connected, it is set to 0x00000200. ECAT_PHYPOLINVERT_IN/OUT is set to true. I also tried setting it to false, but this did not solve the problem.

Both PHYs are configured identical. As EnhancedLink works for port0, I would assume that the configuration should be ok.

So obviously your findings are correct. There is a problem with EnhancedLink detection, but only for port1... How can we identify the reason for this problem?

Best regards
Christian

Hi Christian,

Christian Br said:

There is a problem with EnhancedLink detection, but only for port1... How can we identify the reason for this problem?

• If the software is aligned identically for both the PHYs, could be an issue with Hardware configuration maybe. Make sure you have connected PRx_MII0_RXLINK and PRx_MII1_RXLINK and additionally, could you probe PRx_MII1_RXLINK pin and see if it is getting updated with the link status?
• The fact that daisy chain (Port1 Tx <> Port0 Rx) works fine still puzzles me. Will check further on this for possible issues.

Regards,
Aaron

Hi Aaron,

Aaron Thomas said:

If the software is aligned identically for both the PHYs, could be an issue with Hardware configuration maybe. Make sure you have connected PRx_MII0_RXLINK and PRx_MII1_RXLINK and additionally, could you probe PRx_MII1_RXLINK pin and see if it is getting updated with the link status?

I just probed MII1_RXLINK link on the PHY side. It is set to high, as soon as I connect the cable. So, as expected...
It connects to PRG1_PRU1_GPO8 on the Sitara. The other PHY (port 0) is connected to PRG1_PRU0_GPO8. This is the pinout for connections between the PHYs and our Sitara:

Aaron Thomas said:

• The fact that daisy chain (Port1 Tx <> Port0 Rx) works fine still puzzles me. Will check further on this for possible issues.

Yep, this is really interesting... Just let me know if I can provide any additional information. Thanks again for your support!

Best regards
Christian

Hi Christian,

Christian Br said:

Just let me know if I can provide any additional information. Thanks again for your support!

• I'll check on this internally and get back to you on possible mismatch that can cause this issue.

Regards,
Aaron