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AM2432: Ethernet PHY Reset Circuit

Hideaki Matsumoto
Genius 9160 points
Part Number: AM2432
Other Parts Discussed in Thread: AM6412, AM6422, AM6442, AM2434

Tool/software:

Hi,

 

My customer has a question about Application Note : “AM6442 , AM6422 , AM6412 and AM2434 Processor Schematic Design Guidelines and Schematic Review Checklist”.

 

The second half in the chapter 7.3.1.4 seems to be the same as the connection on AM64x/AM243x EVM.

On their custom board, the Ethernet PHY is reset only by the GPIO, without an AND gate. There is only turn the power on and off, No warm reset and No EPHY boot.

This is different from the recommendation in the Application Note below, are there any issue or risks ?

 

7.3.1.4 Ethernet PHY Reset

The recommendation is to implement the attached device reset using a 3-input ANDing logic. Processor general

purpose input/output (GPIO) is connected as one of the input to the AND gate with provision for pullup (to

support boot) near to the input and 0Ω to isolate the GPIO for testing or debug. The other two AND gate inputs

are the main domain POR (cold reset) status output (PORz_OUT) and main domain warm reset status output

(RESETSTATz) signals.

If a dual input AND gate is used, PORz_OUT or RESETSTATz can be connected as one of the input along with

the processor GPIO input as the second input based on the use case.

 

 

Thanks and regards,

Hideaki

  • 0
    TI__Guru**** 193079 points

    Hello Hideaki

    Thank you for the query.

    Hideaki Matsumoto said:
    On their custom board, the Ethernet PHY is reset only by the GPIO, without an AND gate. There is only turn the power on and off, No warm reset and No EPHY boot.

    I am not sure i understand the inputs.

    Are you connecting an SOC IO to the EPHY reset?

    Now sure how this would turn off power to EPHY.

    It would help if you can share the schematics for me to review.

    The ANDing logic is to support latching of the strap configurations by the EPHY when the SOC is getting reset.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Genius 9160 points

    Hi Sreenivassa,

    Thank you for your response. I've received some feedbacks to your questions from the customer. Please check below. 

     

    The Application note recommends to implement the attached device reset using a 3-input ANDing logic for GPIO, PORz_OUT and RESETSTATz signals, but the customer doesn’t use AND gate logic. Only GPIO of AM243x is used for Ethernet PHY Reset (release).

     

    Here is the block diagram of power rails.

     

    Power for AM243x and Ethernet PHY are supplied by PMIC from 5V.

    By turning off 5V for PMIC or making Enable Low, both Ethernet PHY and AM243x are turned off.

     

    Is there any problem on this customer’s design ?

     

    Thanks and regards,

    Hideaki

  • 0 in reply to Hideaki Matsumoto
    TI__Guru**** 193079 points

    Hello Hideaki

    Thank you for the inputs.

    Let me review and comeback

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Guru**** 193079 points

    Hello Hideaki

    Thank you.

    The block diagram does not include the PMIC OPN used.

    If the question is can you connect only SOC IO to the EPHY reset, you should be able to pulldown the EPHY reset.

    If there are any pin strap that are required to be latched, the recommendation is to release the EPHY reset before the SOC Ethernet interface peripheral is initialized.

    Regards,

    Sreenivasa