MSPM0G1507: Internal oscillator at 80 MHz

Geoffrey Ficara said:

Is it the recommended way to clock the MCU at 80 MHz without using an external oscillator?

You are using sysosc to source syspll.

Your configuration is correct, please refer to Datasheet 7.9.3 System Phase Lock Loop (SYSPLL)

Here is the configuration from my side:

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/7043.empty.syscfg

Geoffrey Ficara said:

Is the accuracy (7.9.1.1 SYSOSC Typical Frequency Accuracy from the datasheet) impacted going through the PLL ? 

Yes.

Because sysosc is the source of syspll.

Hi, 

My use case is price sensitive, therefore I don't want to use an external crystal, which you did in your example.

1) Thank you for confirming that my configuration is correct. Do you confirm that this is the best configuration possible to maximize the accuracy ? 

2) I struggle to understand how to determine the accuracy at the output out of the PLL, can you elaborate ?

Regards

Geoffrey 

Geoffrey Ficara said:

Do you confirm that this is the best configuration possible to maximize the accuracy ? 

Accuracy is mainly based on SYSOSC.

You can enable SYSOSC's FCL function with external Rosc.

For the FCL accuracy, please refer to datasheet - 7.9.1 System Oscillator (SYSOSC) - SYSOSC accuracy when frequency correction loop (FCL) is enabled with ROSC resistor put at ROSC pin, for factory trimmed frequencies

Geoffrey Ficara said:

2) I struggle to understand how to determine the accuracy at the output out of the PLL, can you elaborate ?

The time accuracy is mainly based on SYSOSC's accuracy.

Hi, 

Yes I saw these information, which are coherent. 

To be more specific, I need a total accuracy < +/-2% over the entire temp range -40 to 125°C. 

1) Using the external ROSC seems to give enough margin 

2) Using the internal ROSC could be an option too but there is no margin. You said that the accuracy mainly depends on the SYSOSC but in this case I still need to understand how the PLL will affect the accuracy to determine if option 2 is viable. Does the PLL increase the inaccuracy to +/-0.1% ? Less than that ?

Regards

Geoffrey  

This this related to PLL itself.

Geoffrey Ficara said:

Does the PLL increase the inaccuracy to +/-0.1% ? Less than that ?

In the normal work status, or PLL locked status, SYSPLL output clock will follow the input clock reference (SYSOSC), this will add some jitter to SYSPLL, and accuracy is also following the the SYSOSC.

I am not the expert of PLL, I think SYSPLL won't increase inaccuracy lager than 0.1%, since jitter error itself will be kept within 100ps in locked phase.

Another tips from my side, please try to set VCO to 160MHz.

Hi, 

Thanks for your help. 

1) Would it be possible to have a confirmation regarding the PPL inaccuracy ? 

2) Alright, what is the reason ?

Regards

Geoffrey 

Can not confirm SYSPLL's accuracy from my side, or from datasheet.

Based on common knowledge, SYSPLL's accuracy sources from SYSPLL reference clock, SYSOSC.

Any VCO between this range is OK