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MSPM0G3519: FRANGE setting

rafael flores
Intellectual 340 points
Part Number: MSPM0G3519
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Hi, I have a question about the FRANGE setting. In all the examples I see:

SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
{

	//Low Power Mode is configured to be SLEEP0
    DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);

    DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
    /* Set default configuration */
    DL_SYSCTL_disableHFXT();
    DL_SYSCTL_disableSYSPLL();
    DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_1);
    DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER_DISABLE);

}

static const DL_ADC12_ClockConfig gADC12_0ClockConfig = {
    .clockSel       = DL_ADC12_CLOCK_ULPCLK,
    .divideRatio    = DL_ADC12_CLOCK_DIVIDE_8,
    .freqRange      = DL_ADC12_CLOCK_FREQ_RANGE_24_TO_32,
};

Shouldn't the FRANGE setting be DL_ADC12_CLOCK_FREQ_RANGE_4_TO_8?

  • +1
    TI__Prodigy 655 points

    Hi Rafael,

    freqRange refers to the source clock speed and does not factor in the divide ratio. In this case, since ULPCLK is default set to 32MHz, the FRANGE captures that value. You can see this reflected when you modify the clock speeds in sysconfig (in this example, I set ULPCLK to 40MHz):

    In my understanding, this is because the ADC needs an accurate FRANGE for the source clock in conjunction with the resolution to determine the maximum amount of cycles each conversion should take before signaling end of conversion (EOC). The clkdiv is used after the fact to determine the actual sample clock parameters.

    You can find more details on this operation and the registers in the technical reference manual section 12.2.5 (pg 1131)

    Best,

    Sam

  • 0 in reply to Sam Faris
    Intellectual 340 points

    Thank you for the clarification