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RM57L843: EMIF Issue

Part Number: RM57L843

Tool/software:

Hi,

I am currently facing an issue with EMIF during write operations. My objective is to achieve the maximum speed of EMIF, and for that, I have configured the lowest possible timings in the Asynchronous Configuration Register (CE2CFG). Specifically, I have set the write and read setup, strobe, and hold times to 0.

Based on this configuration, the expected time to write one byte of data to external asynchronous memory should be approximately 40 ns for both read and write operations. However, in practice, I am observing that the write operation takes around 220 ns, which is significantly higher than the configured value. On the other hand, the read timing is close to the expected value at approximately 44 ns.

I have attached the logic analyzer capture and the EMIF configuration screenshot for your reference.

Could you please help me identify the cause of this discrepancy and suggest possible solutions to achieve the desired write performance?

Thanks,

Regards,

Veerappan P.

  • Hi Veerappan,

    I am working on your issue now, will try to provide my updates as soon as possible.

    --
    Thanks & regards,
    Jagadish.

  • Hi Veerappan,

    I think this the datasheet of the memory device that you are using:

    Datasheet.Directory: Sale BU-64843U8-E02 - Global Supply Chains, Offer Electronic Components, Industrial Automation, Process Automation.

    If this is true, then according to this device the max supported clock is 20Mhz only:

    And here they are mentioning that the write access can be upto 570ns:

    So, i am suspecting that slave device is too slow not the master of EMIF. I think this is impacting the throughput.

    --
    Thanks & regards,
    Jagadish.

  • Hi Jagadish,

    Sorry for the late reply — I was out of the station for six days.

    Just to clarify, this thread is about a different topic. We are not using the BU-64843U8-E02 here. Our goal in this case is to achieve the maximum data rate for the EMIF interface. Here, the slave device is an FPGA.

    The MIL-1553 issue we discussed was part of a different thread. The issue is when reading data from slave device's not only the MIL 1553 IC, other slave devices like RTC NVRAM, MRAM, when I assert the emif_nwait signal, it enters into data entry abort. We will discuss in that thread.

    Thanks,

    Regards,

    Veerappan P.

  • Hi Veerappan,

    I did some analysis on your generated waveforms and found this:

    On your generated waveforms, the setup and strobe periods are very less, and they are equal to the read operation timings. And only the hold period is more as compared with read operation. For more details about the definitions of these timings refer below section in TRM:

    According to TRM this hold period can only be varied by two parameters:

    1. W_HOLD, in write cycle this W_HOLD value decides the period of the hold time:

    Verify the value that you configured in this field.

    2. In NAND flash mode if we enable the page mode, then depends on the pages it will extend the hold period.

    I think this should not be applicable for your case, however, check it once.

    Apart from these two there is no other way to extend the Hold period by the EMIF module, if you found still, it is extending even though you didn't enable above two, then it must be FPGA which is externally also controlling the CS line, otherwise i don't think anything for extended hold period.

    --
    Thanks & regards,
    Jagadish.