AM263P4: Cortex-R5F Processor Boot

Hi Olivier,

Olivier Hepler said:

was reading on AMDs website about the arm cortex r5f boot instructions and saw that these are the configuration steps required before an application is run:

1. Program vector table base for exception handling
2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, abort, system)
3. Disable instruction cache, data cache and MPU
4. Invalidate instruction and data cache
5. Configure MPU with short descriptor translation table format and program base address of translation table
6. Enable data cache, instruction cache and MPU
7. Enable Floating point unit
8. Transfer control to _start which clears BSS sections and jumping to main application

Yes this is correct, even for our AMR r%F SoC we do the same stuff. But for microcontrollers, this would be part of the what we call happens before main.

A good article I found on web here: link

Thanks for the help.

So the cint_00 entry point is a combination of _start and all the other r5f configuration steps listed below?

1. Program vector table base for exception handling
2. Program stack pointer for various modes (IRQ, FIQ, supervisor, undefine, abort, system)
3. Disable instruction cache, data cache and MPU
4. Invalidate instruction and data cache
5. Configure MPU with short descriptor translation table format and program base address of translation table
6. Enable data cache, instruction cache and MPU
7. Enable Floating point unit
8. Transfer control to _start which clears BSS sections and jumping to main application

Is this part of what we flash onto the board when flashing our sbl?

Yes this is part of SBL code.

Does "part of the SBL code" mean that it is called from the SBL main function?

Ok that makes sense. thank you I appreciate all the info!