AM2612: Enet layer2 RGMII 1G communication Rx is Ok, but Tx is Nok with incorrect tx clock frequency 6.25MHz.

Yang Lingyun

Prodigy 50 points

Part Number: AM2612
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Dear TI experts,

We encountered a problem during testing custom board enet layer 2 communication with AM2612:

The environment is:

SDK: mcu_plus_sdk_am261x_10_00_01_10

Syscfg: sysconfig_1.23.0

ti-cgt-armllvm_4.0.1.LTS

ccs1281

The problem is:

Application boot from FLASH. Boot mode is OSPI 1S. We use RGMII 1G to communication. Application can receive layer2 messages and send out it, but tx messages can't be captured by Wireshark monitoring, .

With same application running by JTAG, both rx and tx messages can be captured by Wireshark.

We measured rx and tx RGMII clock and found rx freq is 125MHz, tx freq is 6.25MHz when boot from flash and both rx and tx freq is 125MHz when using JTAG.

And we printed some registers about RGMII:

JTAG：

MSS_RCM_MSS_RGMII_CLK_DIV_VAL      0x111
MSS_RCM_CPSW_5_50_250_CLK_MUX_CTRL 0x333
MSS_RCM_MSS_CPTS_CLK_SRC_SEL       0x222
MSS_RCM_MSS_CPTS_CLK_DIV_VAL       0x0

FLASH:

MSS_RCM_MSS_RGMII_CLK_DIV_VAL      0x111
MSS_RCM_CPSW_5_50_250_CLK_MUX_CTRL 0x0
MSS_RCM_MSS_CPTS_CLK_SRC_SEL       0x222
MSS_RCM_MSS_CPTS_CLK_DIV_VAL       0x0

You can see the register MSS_RCM_CPSW_5_50_250_CLK_MUX_CTRL(i.e. 0x53208220) value is incorrect when boot from flash.

I tried to set the register in application source code:

Then the problem is solved. Tx and rx messages can be captured by wireshark when boot from flash.

But my concern is: the changes is not enough. Has any other initialization work been forgotten? Could you please have a complete check for clock initialization during SBL period?

The following structure is abstracted from ti_power_clock_config.c for your reference.

SOC_ModuleClockFrequency gSocModulesClockFrequency[] = {
{ SOC_RcmPeripheralId_I2C, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT0, 48000000},

{ SOC_RcmPeripheralId_ICSSM0_CORE, SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0, 225000000},
{ SOC_RcmPeripheralId_ICSSM0_UART0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, 160000000},
{ SOC_RcmPeripheralId_ICSSM1_CORE, SOC_RcmPeripheralClockSource_DPLL_ETH_HSDIV0_CLKOUT0, 225000000},
{ SOC_RcmPeripheralId_ICSSM1_UART0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, 160000000},

{ SOC_RcmPeripheralId_CPTS, SOC_RcmPeripheralClockSource_SYS_CLK, 250000000},

{ SOC_RcmPeripheralId_LIN0_UART0, SOC_RcmPeripheralClockSource_DPLL_PER_HSDIV0_CLKOUT2, 160000000},

{ SOC_MODULES_END, SOC_MODULES_END, SOC_MODULES_END },
};

Best Regards,

3 months ago

0 Shaunak Deshpande 3 months ago

TI__Genius 16332 points

Hi LY,

It does seem like the SBL is missing some clock configuration. Let me have this thoroughly checked with the team. To help me understand this better, can you please answer the following:

1. What RGMII PHY are you using with AM261x-LP

2. Is the issue resolved and application working fine when you write "0x333" to the MSS_RCM_CPSW_5_50_250_CLK_MUX_CTRL register? Or you see any more errors? I also recommend you to check the CPSW stats and see if there are any packet drops/ CRC errors being observed. This is to make sure you don't see unexpected packet drops.

Meanwhile I will ask the team to check the clock configurations.

Regards,
Shaunak

0 Shaunak Deshpande 3 months ago

TI__Genius 16332 points

Hi LY,

adding to my reply above,

Q1. Can you please share your example.syscfg for your RGMII L2 application as well?

Q2. Since this is a custom board design, you can get your schematics verified by TI Experts as well. Let me know if you need help on this front.

Regards,
Shaunak

0 Yang Lingyun 3 months ago in reply to Shaunak Deshpande

Prodigy 50 points

Q1:

/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "AM261x_ZFG" --part "AM2612" --package "ZFG" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM261x@10.00.01"
 * @v2CliArgs --device "AM2612" --package "NFBGA (ZFG)" --context "r5fss0-0" --product "MCU_PLUS_SDK_AM261x@10.00.01"
 * @versions {"tool":"1.23.0+4000"}
 */

/**
 * Import the modules used in this configuration.
 */
const eeprom             = scripting.addModule("/board/eeprom/eeprom", {}, false);
const eeprom1            = eeprom.addInstance();
const ethphy_cpsw_icssg  = scripting.addModule("/board/ethphy_cpsw_icssg/ethphy_cpsw_icssg", {}, false);
const ethphy_cpsw_icssg1 = ethphy_cpsw_icssg.addInstance();
const edma               = scripting.addModule("/drivers/edma/edma", {}, false);
const edma1              = edma.addInstance();
const epwm               = scripting.addModule("/drivers/epwm/epwm", {}, false);
const epwm1              = epwm.addInstance();
const epwm2              = epwm.addInstance();
const gpio               = scripting.addModule("/drivers/gpio/gpio", {}, false);
const gpio1              = gpio.addInstance();
const gpio2              = gpio.addInstance();
const gpio3              = gpio.addInstance();
const gpio4              = gpio.addInstance();
const gpio5              = gpio.addInstance();
const gpio6              = gpio.addInstance();
const gpio7              = gpio.addInstance();
const gpio8              = gpio.addInstance();
const gpio9              = gpio.addInstance();
const gpio10             = gpio.addInstance();
const gpio11             = gpio.addInstance();
const gpio12             = gpio.addInstance();
const gpio13             = gpio.addInstance();
const gpio14             = gpio.addInstance();
const gpio15             = gpio.addInstance();
const gpio16             = gpio.addInstance();
const gpio17             = gpio.addInstance();
const gpio18             = gpio.addInstance();
const i2c                = scripting.addModule("/drivers/i2c/i2c", {}, false);
const i2c1               = i2c.addInstance();
const i2c2               = i2c.addInstance();
const i2c3               = i2c.addInstance();
const pruicss            = scripting.addModule("/drivers/pruicss/pruicss", {}, false);
const pruicss1           = pruicss.addInstance();
const pruicss2           = pruicss.addInstance();
const clock              = scripting.addModule("/kernel/dpl/clock");
const debug_log          = scripting.addModule("/kernel/dpl/debug_log");
const dpl_cfg            = scripting.addModule("/kernel/dpl/dpl_cfg");
const mpu_armv7          = scripting.addModule("/kernel/dpl/mpu_armv7", {}, false);
const mpu_armv71         = mpu_armv7.addInstance();
const mpu_armv72         = mpu_armv7.addInstance();
const mpu_armv73         = mpu_armv7.addInstance();
const mpu_armv74         = mpu_armv7.addInstance();
const mpu_armv75         = mpu_armv7.addInstance();
const general            = scripting.addModule("/memory_configurator/general", {}, false);
const general1           = general.addInstance();
const region             = scripting.addModule("/memory_configurator/region", {}, false);
const region1            = region.addInstance();
const section            = scripting.addModule("/memory_configurator/section", {}, false);
const section1           = section.addInstance();
const section2           = section.addInstance();
const section3           = section.addInstance();
const section4           = section.addInstance();
const section5           = section.addInstance();
const section6           = section.addInstance();
const section7           = section.addInstance();
const section8           = section.addInstance();
const section9           = section.addInstance();
const section10          = section.addInstance();
const enet_cpsw          = scripting.addModule("/networking/enet_cpsw/enet_cpsw", {}, false);
const enet_cpsw1         = enet_cpsw.addInstance();

/**
 * Write custom configuration values to the imported modules.
 */
eeprom1.$name      = "CONFIG_EEPROM0";
eeprom1.i2cAddress = 0x54;

ethphy_cpsw_icssg1.$name              = "CONFIG_ENET_ETHPHY0";
ethphy_cpsw_icssg1.phySelect          = "CUSTOM";
ethphy_cpsw_icssg1.customDeviceName   = "mxl86111";
ethphy_cpsw_icssg1.isStrappedPhy      = true;
ethphy_cpsw_icssg1.skipExtendedConfig = true;
scripting.suppress("Warning : Ethphy device is not linked to a network peripheral", ethphy_cpsw_icssg1);

edma1.$name                 = "CONFIG_EDMA0";
edma1.edmaRmDmaCh[0].$name  = "CONFIG_EDMA_RM0";
edma1.edmaRmQdmaCh[0].$name = "CONFIG_EDMA_RM1";
edma1.edmaRmTcc[0].$name    = "CONFIG_EDMA_RM2";
edma1.edmaRmParam[0].$name  = "CONFIG_EDMA_RM3";

epwm1.$name          = "HSHB1";
epwm1.EPWM.$assign   = "EPWM3";
epwm1.EPWM.A.$assign = "GPIO49";
epwm1.EPWM.B.$assign = "GPIO50";

epwm2.$name          = "HSHB2";
epwm2.epwmGroup      = "EPWM_GROUP1";
epwm2.EPWM.$assign   = "EPWM2";
epwm2.EPWM.A.$assign = "GPIO47";
epwm2.EPWM.B.$assign = "GPIO48";

gpio1.$name          = "LED0";
gpio1.pinDir         = "OUTPUT";
gpio1.GPIO_n.$assign = "GPIO0";

gpio2.$name          = "LED1";
gpio2.pinDir         = "OUTPUT";
gpio2.GPIO_n.$assign = "GPIO1";

gpio3.$name          = "PCB_VER0";
gpio3.GPIO_n.$assign = "GPIO5";

gpio4.$name          = "PCB_VER1";
gpio4.GPIO_n.$assign = "GPIO6";

gpio5.$name          = "PCB_VER2";
gpio5.GPIO_n.$assign = "GPIO11";

gpio6.$name          = "PCB_VER3";
gpio6.GPIO_n.$assign = "GPIO14";

gpio7.$name          = "PCBA_VER0";
gpio7.GPIO_n.$assign = "GPIO15";

gpio8.$name          = "PCBA_VER1";
gpio8.GPIO_n.$assign = "GPIO16";

gpio9.$name          = "PCBA_VER2";
gpio9.GPIO_n.$assign = "GPIO17";

gpio10.$name          = "SLOT0";
gpio10.GPIO_n.$assign = "GPIO24";

gpio11.$name          = "SLOT1";
gpio11.GPIO_n.$assign = "GPIO23";

gpio12.$name          = "SLOT2";
gpio12.GPIO_n.$assign = "GPIO21";

gpio13.$name          = "SLOT3";
gpio13.GPIO_n.$assign = "GPIO25";

gpio14.$name          = "PHY_RESET";
gpio14.pinDir         = "OUTPUT";
gpio14.defaultValue   = "1";
gpio14.pu_pd          = "pu";
gpio14.GPIO_n.$assign = "GPIO22";

gpio15.$name          = "SLOT4";
gpio15.GPIO_n.$assign = "GPIO19";

gpio16.$name          = "PRESENT_N";
gpio16.pu_pd          = "pu";
gpio16.GPIO_n.$assign = "GPIO26";

gpio17.$name          = "DO_PWR_CDE";
gpio17.pu_pd          = "pd";
gpio17.pinDir         = "OUTPUT";
gpio17.GPIO_n.$assign = "GPIO51";

gpio18.$name          = "GPIO_OSPI_RST";
gpio18.pinDir         = "OUTPUT";
gpio18.GPIO_n.$assign = "GPIO20";

i2c1.$name               = "EEPROM";
i2c1.ownTargetAddr       = 0x54;
eeprom1.peripheralDriver = i2c1;
i2c1.I2C.$assign         = "I2C0";
i2c1.I2C.SCL.$assign     = "GPIO135";
i2c1.I2C.SDA.$assign     = "GPIO134";
i2c1.I2C_child.$name     = "drivers_i2c_v1_i2c_v1_template0";

i2c2.$name           = "A1006";
i2c2.I2C.$assign     = "I2C1";
i2c2.I2C.SCL.$assign = "GPIO131";
i2c2.I2C.SDA.$assign = "GPIO130";
i2c2.I2C_child.$name = "drivers_i2c_v1_i2c_v1_template1";

i2c3.$name           = "PMIC";
i2c3.I2C.$assign     = "I2C2";
i2c3.I2C.SCL.$assign = "GPIO83";
i2c3.I2C.SDA.$assign = "GPIO84";
i2c3.I2C_child.$name = "drivers_i2c_v1_i2c_v1_template2";

pruicss1.$name                                                                     = "CONFIG_PRU_ICSS0";
pruicss1.AdditionalICSSSettings[0].$name                                           = "CONFIG_PRU_ICSS_IO0";
pruicss1.AdditionalICSSSettings[0].PruGPIO.create(1);
pruicss1.AdditionalICSSSettings[0].PruGPIO[0].$name                                = "CONFIG_PRU_ICSS_GPIO0";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].$assign                 = "PRU-ICSS0";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO7.$assign  = "GPIO124";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO7.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO11.$assign = "GPIO99";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO11.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO12.rx      = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO12.$assign = "GPIO100";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO12.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO15.$assign = "GPIO98";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO15.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO0.rx       = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO0.$assign  = "GPIO93";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO0.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO1.$assign  = "GPIO94";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO1.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO6.$assign  = "GPIO91";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO6.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO2.$assign  = "GPIO95";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO2.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO3.$assign  = "GPIO96";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO3.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO4.rx       = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO4.$assign  = "GPIO92";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO4.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO16.rx      = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO16.$assign = "GPIO97";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO16.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO13.$assign = "GPIO101";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO13.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO14.rx      = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO14.$assign = "GPIO102";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO14.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO5.$assign  = "GPIO87";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO5.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO10.$assign = "GPIO89";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO10.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO9.rx       = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO9.$assign  = "GPIO88";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO9.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO8.$assign  = "GPIO90";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU0_GPIO8.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO5.$assign  = "GPIO103";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO5.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO8.$assign  = "GPIO106";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO8.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO9.$assign  = "GPIO104";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO9.$used    = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO10.rx      = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO10.$assign = "GPIO105";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO10.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO18.$assign = "GPIO120";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO18.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO19.$assign = "GPIO119";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO19.$used   = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO17.rx      = true;
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO17.$assign = "GPIO125";
pruicss1.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS0"].PR0_PRU1_GPIO17.$used   = true;
pruicss1.intcMapping.create(1);
pruicss1.intcMapping[0].$name                                                      = "CONFIG_ICSS0_INTC_MODE1_MAPPING1";
pruicss1.intcMapping[0].event                                                      = "22";
pruicss1.intcMapping[0].channel                                                    = "1";

pruicss2.$name                                                                     = "CONFIG_PRU_ICSS1";
pruicss2.instance                                                                  = "ICSSM1";
pruicss2.AdditionalICSSSettings[0].$name                                           = "CONFIG_PRU_ICSS_IO1";
pruicss2.AdditionalICSSSettings[0].PruGPIO.create(1);
pruicss2.AdditionalICSSSettings[0].PruGPIO[0].$name                                = "CONFIG_PRU_ICSS_GPIO1";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].$assign                 = "PRU-ICSS1";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO0.rx       = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO0.$assign  = "GPIO71";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO0.$used    = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO1.$assign  = "GPIO72";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO1.$used    = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO9.$assign  = "GPIO74";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO9.$used    = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO10.rx      = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO10.$assign = "GPIO123";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO10.$used   = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO20.$assign = "GPIO132";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU0_GPIO20.$used   = true;
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO7.$assign  = "GPIO133";
pruicss2.AdditionalICSSSettings[0].PruGPIO[0]["PRU-ICSS1"].PR1_PRU1_GPIO7.$used    = true;
pruicss2.intcMapping.create(1);
pruicss2.intcMapping[0].$name                                                      = "CONFIG_ICSS1_INTC_MODE1_MAPPING0";
pruicss2.intcMapping[0].event                                                      = "22";
pruicss2.intcMapping[0].channel                                                    = "1";

const soc_ctrl_adc    = scripting.addModule("/drivers/soc_ctrl/v0/subModules/soc_ctrl_adc", {}, false);
const soc_ctrl_adc1   = soc_ctrl_adc.addInstance({}, false);
soc_ctrl_adc1.$name   = "soc_ctrl_adc0";
const soc_ctrl        = scripting.addModule("/drivers/soc_ctrl/soc_ctrl", {}, false);
soc_ctrl.soc_ctrl_adc = soc_ctrl_adc1;

const soc_ctrl_cmpss    = scripting.addModule("/drivers/soc_ctrl/v0/subModules/soc_ctrl_cmpss", {}, false);
const soc_ctrl_cmpss1   = soc_ctrl_cmpss.addInstance({}, false);
soc_ctrl_cmpss1.$name   = "soc_ctrl_cmpss0";
soc_ctrl.soc_ctrl_cmpss = soc_ctrl_cmpss1;

const soc_ctrl_epwm    = scripting.addModule("/drivers/soc_ctrl/v0/subModules/soc_ctrl_epwm", {}, false);
const soc_ctrl_epwm1   = soc_ctrl_epwm.addInstance({}, false);
soc_ctrl_epwm1.$name   = "soc_ctrl_epwm0";
epwm.epwmTbClkSync     = soc_ctrl_epwm1;
soc_ctrl.soc_ctrl_epwm = soc_ctrl_epwm1;

const soc_ctrl_sdfm    = scripting.addModule("/drivers/soc_ctrl/v0/subModules/soc_ctrl_sdfm", {}, false);
const soc_ctrl_sdfm1   = soc_ctrl_sdfm.addInstance({}, false);
soc_ctrl_sdfm1.$name   = "soc_ctrl_sdfm0";
soc_ctrl.soc_ctrl_sdfm = soc_ctrl_sdfm1;

debug_log.enableUartLog            = true;
debug_log.enableCssLog             = false;
debug_log.uartLog.$name            = "CONFIG_UART0";
debug_log.uartLog.UART.$assign     = "UART0";
debug_log.uartLog.UART.RXD.$assign = "GPIO27";
debug_log.uartLog.UART.TXD.$assign = "GPIO28";
debug_log.uartLog.child.$name      = "drivers_uart_v2_uart_v2_template0";

mpu_armv71.$name             = "CONFIG_MPU_REGION0";
mpu_armv71.size              = 31;
mpu_armv71.attributes        = "Device";
mpu_armv71.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv71.allowExecute      = false;

mpu_armv72.$name             = "CONFIG_MPU_REGION1";
mpu_armv72.size              = 15;
mpu_armv72.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv73.$name             = "CONFIG_MPU_REGION2";
mpu_armv73.baseAddr          = 0x80000;
mpu_armv73.size              = 15;
mpu_armv73.accessPermissions = "Supervisor RD+WR, User RD";

mpu_armv74.$name             = "CONFIG_MPU_REGION3";
mpu_armv74.accessPermissions = "Supervisor RD+WR, User RD";
mpu_armv74.baseAddr          = 0x70000000;
mpu_armv74.size              = 21;

mpu_armv75.$name      = "CONFIG_MPU_REGION4";
mpu_armv75.attributes = "NonCached";
mpu_armv75.baseAddr   = 0x70040000;
mpu_armv75.size       = 12;

general1.$name        = "CONFIG_GENERAL0";
general1.heap_size    = 1024;
general1.linker.$name = "TIARMCLANG0";

region1.$name                               = "MEMORY_REGION_CONFIGURATION0";
region1.memory_region.create(7);
region1.memory_region[0].type               = "TCMA";
region1.memory_region[0].$name              = "R5F_VECS";
region1.memory_region[0].auto               = false;
region1.memory_region[0].size               = 0x40;
region1.memory_region[1].type               = "TCMA";
region1.memory_region[1].$name              = "R5F_TCMA";
region1.memory_region[1].size               = 0x7FC0;
region1.memory_region[2].type               = "TCMB";
region1.memory_region[2].size               = 0x8000;
region1.memory_region[2].$name              = "R5F_TCMB";
region1.memory_region[3].$name              = "CPPI_DESC";
region1.memory_region[3].auto               = false;
region1.memory_region[3].size               = 0x4000;
region1.memory_region[3].manualStartAddress = 0x70040000;
region1.memory_region[4].$name              = "OCRAM";
region1.memory_region[4].auto               = false;
region1.memory_region[4].manualStartAddress = 0x70044000;
region1.memory_region[4].size               = 0x13C000;
region1.memory_region[5].type               = "FLASH";
region1.memory_region[5].$name              = "FLASH";
region1.memory_region[5].auto               = false;
region1.memory_region[5].manualStartAddress = 0x60100000;
region1.memory_region[5].size               = 0x80000;
region1.memory_region[6].$name              = "SBL";
region1.memory_region[6].size               = 0x40000;
region1.memory_region[6].auto               = false;

section1.load_memory                  = "R5F_VECS";
section1.group                        = false;
section1.$name                        = "Vector Table";
section1.output_section.create(1);
section1.output_section[0].$name      = ".vectors";
section1.output_section[0].palignment = true;

section2.load_memory                  = "OCRAM";
section2.$name                        = "Text Segments";
section2.output_section.create(5);
section2.output_section[0].$name      = ".text.hwi";
section2.output_section[0].palignment = true;
section2.output_section[1].$name      = ".text.cache";
section2.output_section[1].palignment = true;
section2.output_section[2].$name      = ".text.mpu";
section2.output_section[2].palignment = true;
section2.output_section[3].$name      = ".text.boot";
section2.output_section[3].palignment = true;
section2.output_section[4].$name      = ".text:abort";
section2.output_section[4].palignment = true;

section3.load_memory                  = "OCRAM";
section3.$name                        = "Code and Read-Only Data";
section3.output_section.create(2);
section3.output_section[0].$name      = ".text";
section3.output_section[0].palignment = true;
section3.output_section[1].$name      = ".rodata";
section3.output_section[1].palignment = true;

section4.load_memory                  = "OCRAM";
section4.$name                        = "Data Segment";
section4.output_section.create(1);
section4.output_section[0].$name      = ".data";
section4.output_section[0].palignment = true;

section5.load_memory                             = "OCRAM";
section5.$name                                   = "Memory Segments";
section5.output_section.create(3);
section5.output_section[0].$name                 = ".bss";
section5.output_section[0].output_sections_start = "__BSS_START";
section5.output_section[0].output_sections_end   = "__BSS_END";
section5.output_section[0].palignment            = true;
section5.output_section[1].$name                 = ".sysmem";
section5.output_section[1].palignment            = true;
section5.output_section[2].$name                 = ".stack";
section5.output_section[2].palignment            = true;

section6.load_memory                              = "OCRAM";
section6.$name                                    = "Stack Segments";
section6.output_section.create(5);
section6.output_section[0].$name                  = ".irqstack";
section6.output_section[0].output_sections_start  = "__IRQ_STACK_START";
section6.output_section[0].output_sections_end    = "__IRQ_STACK_END";
section6.output_section[0].input_section.create(1);
section6.output_section[0].input_section[0].$name = ". = . + __IRQ_STACK_SIZE;";
section6.output_section[1].$name                  = ".fiqstack";
section6.output_section[1].output_sections_start  = "__FIQ_STACK_START";
section6.output_section[1].output_sections_end    = "__FIQ_STACK_END";
section6.output_section[1].input_section.create(1);
section6.output_section[1].input_section[0].$name = ". = . + __FIQ_STACK_SIZE;";
section6.output_section[2].$name                  = ".svcstack";
section6.output_section[2].output_sections_start  = "__SVC_STACK_START";
section6.output_section[2].output_sections_end    = "__SVC_STACK_END";
section6.output_section[2].input_section.create(1);
section6.output_section[2].input_section[0].$name = ". = . + __SVC_STACK_SIZE;";
section6.output_section[3].$name                  = ".abortstack";
section6.output_section[3].output_sections_start  = "__ABORT_STACK_START";
section6.output_section[3].output_sections_end    = "__ABORT_STACK_END";
section6.output_section[3].input_section.create(1);
section6.output_section[3].input_section[0].$name = ". = . + __ABORT_STACK_SIZE;";
section6.output_section[4].$name                  = ".undefinedstack";
section6.output_section[4].output_sections_start  = "__UNDEFINED_STACK_START";
section6.output_section[4].output_sections_end    = "__UNDEFINED_STACK_END";
section6.output_section[4].input_section.create(1);
section6.output_section[4].input_section[0].$name = ". = . + __UNDEFINED_STACK_SIZE;";

section7.load_memory                  = "OCRAM";
section7.$name                        = "Initialization and Exception Handling";
section7.output_section.create(3);
section7.output_section[0].$name      = ".ARM.exidx";
section7.output_section[0].palignment = true;
section7.output_section[1].$name      = ".init_array";
section7.output_section[1].palignment = true;
section7.output_section[2].$name      = ".fini_array";
section7.output_section[2].palignment = true;

section8.group                       = false;
section8.load_memory                 = "CPPI_DESC";
section8.type                        = "NOLOAD";
section8.$name                       = "ENET_CPPI_DESC";
section8.output_section.create(1);
section8.output_section[0].$name     = ".bss:ENET_CPPI_DESC";
section8.output_section[0].alignment = 128;

section9.$name                       = "ENET_DMA_PKT_MEMPOOL";
section9.load_memory                 = "OCRAM";
section9.group                       = false;
section9.type                        = "NOLOAD";
section9.output_section.create(1);
section9.output_section[0].$name     = ".bss:ENET_DMA_PKT_MEMPOOL";
section9.output_section[0].alignment = 128;

section10.$name                       = "CONFIG_SECTION0";
section10.load_memory                 = "OCRAM";
section10.output_section.create(1);
section10.output_section[0].$name     = ".bss.filebuf";
section10.output_section[0].alignment = 128;

enet_cpsw1.$name                 = "CONFIG_ENET_CPSW0";
enet_cpsw1.cptsHostRxTsEn        = false;
enet_cpsw1.macport2LinkDuplexity = "ENET_DUPLEX_FULL";
enet_cpsw1.macport1LinkDuplexity = "ENET_DUPLEX_FULL";
enet_cpsw1.macport2LinkSpeed     = "ENET_SPEED_100MBIT";
enet_cpsw1.cptsRftClkFreq        = "CPSW_CPTS_RFTCLK_FREQ_200MHZ";
enet_cpsw1.macport1LinkSpeed     = "ENET_SPEED_1GBIT";
enet_cpsw1.DisableMacPort2       = true;
enet_cpsw1.customBoardEnable     = true;
enet_cpsw1.macAddrConfig         = "Manual Entry";
enet_cpsw1.mdioPollEnMask        = ["0"];
enet_cpsw1.macAddrList           = "02:00:54:00:30:04,02:00:54:00:20:04";
enet_cpsw1.MDIO.$assign          = "MDIO0";
enet_cpsw1.MDIO.MDC.$assign      = "GPIO42";
enet_cpsw1.MDIO.MDIO.$assign     = "GPIO41";
enet_cpsw1.RGMII1.$assign        = "RGMII1";
enet_cpsw1.RGMII1.RD0.$assign    = "GPIO109";
enet_cpsw1.RGMII1.RD1.$assign    = "GPIO110";
enet_cpsw1.RGMII1.RD2.$assign    = "GPIO111";
enet_cpsw1.RGMII1.RD3.$assign    = "GPIO112";
enet_cpsw1.RGMII1.RX_CTL.$assign = "GPIO108";
enet_cpsw1.RGMII1.RXC.$assign    = "GPIO107";
enet_cpsw1.RGMII1.TD0.$assign    = "GPIO115";
enet_cpsw1.RGMII1.TD1.$assign    = "GPIO116";
enet_cpsw1.RGMII1.TD2.$assign    = "GPIO117";
enet_cpsw1.RGMII1.TD3.$assign    = "GPIO118";
enet_cpsw1.RGMII1.TX_CTL.$assign = "GPIO114";
enet_cpsw1.RGMII1.TXC.$assign    = "GPIO113";
enet_cpsw1.RGMII2.RD0.$used      = false;
enet_cpsw1.RGMII2.RD1.$used      = false;
enet_cpsw1.RGMII2.RD2.$used      = false;
enet_cpsw1.RGMII2.RD3.$used      = false;
enet_cpsw1.RGMII2.RX_CTL.$used   = false;
enet_cpsw1.RGMII2.RXC.$used      = false;
enet_cpsw1.RGMII2.TD0.$used      = false;
enet_cpsw1.RGMII2.TD1.$used      = false;
enet_cpsw1.RGMII2.TD2.$used      = false;
enet_cpsw1.RGMII2.TD3.$used      = false;
enet_cpsw1.RGMII2.TX_CTL.$used   = false;
enet_cpsw1.RGMII2.TXC.$used      = false;
enet_cpsw1.txDmaChannel[0].$name = "ENET_DMA_TX_CH0";
enet_cpsw1.rxDmaChannel[0].$name = "ENET_DMA_RX_CH0";

/**
 * Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
 * version of the tool will not impact the pinmux you originally saw.  These lines can be completely deleted in order to
 * re-solve from scratch.
 */
enet_cpsw1.RGMII2.$suggestSolution = "RGMII2";

Q2: Yes, our schematics has been verified by TI experts many times.

0 Yang Lingyun 3 months ago in reply to Shaunak Deshpande

Prodigy 50 points

Hi Shaunak,

We are not able to run ethernet communication with AM261x-LP because the communication board you supplied have some issue. Do you remember!

When I write "0x333", layer 2 communication is Ok and there is no more errors being observed.

0 Shaunak Deshpande 3 months ago in reply to Yang Lingyun

TI__Genius 16332 points

Hi LY,

Yang Lingyun said:
We are not able to run ethernet communication with AM261x-LP because the communication board you supplied have some issue. Do you remember!

Yes, I am aware of the issues we have faced even while integration MX86111 PHY.

Yang Lingyun said:
When I write "0x333", layer 2 communication is Ok and there is no more errors being observed.

Glad to know this works, I will check the syscfg file as well as the missing configurations for clocks in SBL and get back.

Regards.
Shaunak

0 Shaunak Deshpande 3 months ago in reply to Shaunak Deshpande

TI__Genius 16332 points

Hi LY,

There was a clock configuration missing which was causing this issue, If you use the DEV boot mode and load via JTAG, the GEL Scripts take care of the clock config, When you boot the application from flash, the SBL takes care of the clock config, which was missing a step. The code we ported for AM261x was from AM263x and there was a change in the default clock configurations. The 0x000 value worked in case of the other device but the AM261x required the register to be configured as 0x333.

In AM263x, the CPSW RGMII clock select value has to be configured as 0x000 and It is the reset value also. So we did not face any issue in AM263x.

But In AM261x the RGMII Mux select value should be 0x333 to get proper RGMII clock and reset value is 0x000. Because of this RGMII is not working in AM261x.
Now we have added some code change in application to configure the RGMII clock correctly, The SDK v10.02 officially fixes it, but you can also use the below file (replace the existing file at this path): C:\ti\workarea_west\mcu_plus_sdk\source\networking\enet\core\sysconfig\networking\.meta\enet_cpsw\am261x\enet_cpsw_am261x.syscfg.js

Fullscreen 8611.enet_cpsw_am261x.syscfg.js Download

"use strict"; let common = system.getScript("/common"); let pinmux = system.getScript("/drivers/pinmux/pinmux"); let soc = system.getScript(`/networking/soc/networking_${common.getSocName()}`); let device = common.getDeviceName(); //Get packet pool configuration script const pktPoolScript = system.getScript("./enet_pkt_pool_config"); //Get ALE configuration script const aleScript = system.getScript("./enet_cpsw_ale_config"); //Get MDIO configuration script const mdioScript = system.getScript("./enet_cpsw_mdio_config"); //Get Host Port configuration script const hostportScript = system.getScript("./enet_cpsw_hostport_config"); //Get CPTS configuration script const cptsScript = system.getScript("./enet_cpsw_cpts_config"); //Get MAC Port configuration script const macportScript = system.getScript("./enet_cpsw_macport_config"); const utilsScript = system.getScript("./../../common/enet_cpsw_utils"); const pinMuxScript = system.getScript("./enet_cpsw_am261x_pinmux"); const enet_cpsw_pinmux_config = { name: "pinmuxConfig", displayName: "Pinmux config", longDescription: "Configuration of pinmux for CPSW", collapsed:true, config: [ ], }; const enet_cpsw_cpdma_channel_config = { name: "cpdmaChConfig", displayName: "DMA channel config", longDescription: "Configuration of Tx/Rx DMA channels", collapsed:true, config: [ ], }; const enet_cpsw_lwipIf_config = { name: "lwipIfConfig", displayName: "LWIP Interface config", longDescription: "Configuration of LWIP Interface", collapsed:true, config: [ ], }; const enet_cpsw_system_config = { name: "cpswSystemConfig", displayName: "System integration config", longDescription: "System integration related configuration", collapsed:true, config: [ { name: "McmEnable", description: "Flag to enable multi-client manager. Required for multi-core, multiple Enet client use cases", displayName: "Mcm Enable", default: false, }, { name: "ExternalPhyMgmtEnable", description: "Flag to enable phy management in application. The enet driver internal phy functions including phy state machine is bypassed in this mode", displayName: "External Phy Management Enable", default: false, onChange:function (inst, ui) { if(inst.ExternalPhyMgmtEnable == true) { ui.macport1LinkSpeed.hidden = true; ui.macport1LinkDuplexity.hidden = true; ui.macport2LinkSpeed.hidden = true; ui.macport2LinkDuplexity.hidden = true; } else{ ui.macport1LinkSpeed.hidden = false; ui.macport1LinkDuplexity.hidden = false; ui.macport2LinkSpeed.hidden = false; ui.macport2LinkDuplexity.hidden = false; } } }, { name: "RtosVariant", description: "Select FreeRTOS or No RTOS", displayName: "RTOS Variant", default: "FreeRTOS", options: [ { name: "FreeRTOS", displayName: "FreeRTOS", }, { name: "NoRTOS", displayName: "No RTOS (Bare Metal)", }, ], }, { name: "macAddrConfig", description: "MAC address to set in the driver. 'Auto Assign shall select the address automatiically from EEPROM and/or EFUSES. 'Manual Entry' will allow to input MAC address", displayName: "MAC Address Assignment Method", onChange:function (inst, ui) { if(inst.macAddrConfig === "Auto Assign") { ui.macAddrList.hidden = true; } else { ui.macAddrList.hidden = false; } }, options: [ { name: "Auto Assign", }, { name: "Manual Entry", }, ], default: "Auto Assign", }, { name: "macAddrList", description: "MAC address to set in the driver. Enter MAC address. Seperate multiple MAC address with comma. Eg.: aa:bb:bb:cc:dd:ee,01:22:33:aa:bb:ee", displayName: "MAC Address List", default: "70:ff:76:1d:ec:f2,70:ff:76:1d:ec:e3", hidden: true, }, { name: "AppLinkUpPortMask", description: "Application config to determine which macPorts should be polled for linkup to indicate link is up.Applicable in multi port scenario only", displayName: "AppLinkUpPortMask Config", default: "ANY_PORT", options: [ { name: "ALL_PORTS", }, { name: "ANY_PORT", }, ], }, ], }; const enet_cpsw_board_config = { name: "cpswBoardConfig", displayName: "Board Config", longDescription: "Board specific configuration", collapsed:true, config: [ { name: "customBoardEnable", description: "Enable Custom Board Configuration", displayName: "Custom Board", longDescription: "Configuration for custom board that are not supported out of box in MCU+ SDK", default: false, }, ], }; function getInterfaceNameList(inst) { return pinMuxScript.getInterfaceNameList(inst); } function pinmuxRequirements(inst) { return pinMuxScript.pinmuxRequirements(inst); } function getPeripheralPinNames(inst) { return pinMuxScript.getPeripheralPinNames(inst); } function getEnetClockConfig(device_name) { var enet_clock_config; if (device_name === "am261x-lp") { enet_clock_config = { clockIds : [ "SOC_RcmPeripheralId_CPTS", "SOC_RcmPeripheralId_CPSW_5_50_250"], clockFrequencies: [ { moduleId: "SOC_RcmPeripheralId_CPTS", clkId : "SOC_RcmPeripheralClockSource_SYS_CLK", clkRate : 250000000, }, { moduleId: "SOC_RcmPeripheralId_CPSW_5_50_250", clkId : "SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1", clkRate : 500000000, }, ], } } else if (device_name === "am261x-som") { enet_clock_config = { clockIds : [ "SOC_RcmPeripheralId_CPTS", , "SOC_RcmPeripheralId_CPSW_5_50_250"], clockFrequencies: [ { moduleId: "SOC_RcmPeripheralId_CPTS", clkId : "SOC_RcmPeripheralClockSource_SYS_CLK", clkRate : 200000000, }, { moduleId: "SOC_RcmPeripheralId_CPSW_5_50_250", clkId : "SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT1", clkRate : 500000000, }, ], } } return enet_clock_config; } function getClockEnableIds(instance) { let instConfig = getEnetClockConfig(device); return instConfig.clockIds; } function getClockFrequencies(inst) { let instConfig = getEnetClockConfig(device); return instConfig.clockFrequencies; } function getDmaInterface(instance) { let cpswInstInfo = getCpswInstInfo(instance); return cpswInstInfo.dmaIf; } function getInstIdTable(instances) { let tbl = '{ ' for (var i = 0; i < instances.length; i++) { tbl += '{'; var matchedInst = getCpswInstInfo(instances[i]) tbl += i + ', ' + matchedInst.enetType + ', ' + matchedInst.instId tbl += '}, ' } tbl += '}' return tbl; } function getMiiConfig(instance) { const cpswMiiConfigMap = new Map( [ ["RGMII",{layerType:"ENET_MAC_LAYER_GMII", variantType:"ENET_MAC_VARIANT_FORCED", sublayerType:"ENET_MAC_SUBLAYER_REDUCED"}], ["RMII", {layerType:"ENET_MAC_LAYER_MII", variantType:"ENET_MAC_VARIANT_NONE", sublayerType:"ENET_MAC_SUBLAYER_REDUCED"}], ["MII", {layerType:"ENET_MAC_LAYER_MII", variantType:"ENET_MAC_VARIANT_NONE", sublayerType:"ENET_MAC_SUBLAYER_STANDARD"}], ],) return cpswMiiConfigMap.get(instance.phyToMacInterfaceMode); } function getCpswInstInfo(instance) { const cpswInstInfoMap = new Map( [ ['am261x',{enetType: 'ENET_CPSW_3G', numMacPorts: '2', instId: '0', dmaIf:'ENET_SOC_HOSTPORT_DMA_TYPE_CPDMA', macPortList:['ENET_MAC_PORT_1', 'ENET_MAC_PORT_2']}], ], ); let instInfo = cpswInstInfoMap.get(common.getSocName()); instInfo.macPortList = instInfo.macPortList.filter(function(macPort, index,arr){ let includeEntry = true; if ((macPort === 'ENET_MAC_PORT_1') && (instance.DisableMacPort1 === true)) { includeEntry = false; } if ((macPort === 'ENET_MAC_PORT_2') && (instance.DisableMacPort2 === true)) { includeEntry = false; } return includeEntry; }); instInfo.numMacPorts = instInfo.macPortList.length; return instInfo; } function getBoardConfigTemplateInfo() { const boardConfigTemplate = new Map( [ ['am261x',{Cfile: "/board/ethphy_cpsw_icssg/templates/am261x/enet_board_cfg.c.xdt", Header: "/board/ethphy_cpsw_icssg/templates/am261x/enet_board_cfg.h.xdt"}], ], ); return boardConfigTemplate.get(common.getSocName()); } function getSocConfigTemplateInfo() { const socConfigTemplate = new Map( [ ['am261x',{Cfile: "/networking/enet_cpsw/templates/am261x/enet_soc_cfg.c.xdt"}], ], ); return socConfigTemplate.get(common.getSocName()); } function getPacketsCount(instance, channelType) { let totalNumPackets = 0; let driverVer = soc.getDriverVer("enet_cpsw"); let dma_ch_instances; let module_dma_ch; if (channelType === "TX") { dma_ch_instances = instance.txDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_tx_channel`]; } else { dma_ch_instances = instance.rxDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_rx_channel`]; } for(let ch = 0; ch < dma_ch_instances.length; ch++) { let ch_instance = dma_ch_instances[ch]; let ch_config = module_dma_ch.getInstanceConfig(ch_instance); totalNumPackets += ch_config.PacketsCount; } return totalNumPackets; } function getChannelCount(instance, channelType) { let totalNumChannels = 0; let driverVer = soc.getDriverVer("enet_cpsw"); let dma_ch_instances; let module_dma_ch; if (channelType === "TX") { dma_ch_instances = instance.txDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_tx_channel`]; } else { dma_ch_instances = instance.rxDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_rx_channel`]; } for(let ch = 0; ch < dma_ch_instances.length; ch++) { let ch_instance = dma_ch_instances[ch]; let ch_config = module_dma_ch.getInstanceConfig(ch_instance); totalNumChannels++; } return totalNumChannels; } function getTxPacketsCount(instance) { return getPacketsCount(instance, "TX"); } function getRxPacketsCount(instance) { return getPacketsCount(instance, "RX"); } function getTxChannelCount(instance) { return getChannelCount(instance, "TX"); } function getRxChannelCount(instance) { return getChannelCount(instance, "RX"); } function getNumCpdmaDesc(instance) { /* Tx packet requires Two Tx scatter gather segments + 1 csum offload descriptor */ const txDesc2PacketScalingFactor = 3; /* Rx packet requires only one desc per packet till scatter gather is supported. * Csum info is at end of packet and no cpdma desc is used */ const rxDesc2PacketScalingFactor = 1; let cpdmaNumDesc = (rxDesc2PacketScalingFactor * getRxPacketsCount(instance)) + (txDesc2PacketScalingFactor * getTxPacketsCount(instance)); return cpdmaNumDesc; } function getChannelConfig(instance, channelType, chTypeInstNum) { let driverVer = soc.getDriverVer("enet_cpsw"); let dma_ch_instances; let module_dma_ch; if (channelType === "TX") { dma_ch_instances = instance.txDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_tx_channel`]; } else { dma_ch_instances = instance.rxDmaChannel; module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_rx_channel`]; } let channelCfgArray = new Array(); for(let ch = 0; ch < dma_ch_instances.length; ch++) { let ch_instance = dma_ch_instances[ch]; let ch_config = module_dma_ch.getInstanceConfig(ch_instance); channelCfgArray.push(ch_config); } return channelCfgArray[chTypeInstNum]; } function getDefaultPacketCount(channelType) { let driverVer = soc.getDriverVer("enet_cpsw"); let module_dma_ch; if (channelType === "TX") { module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_tx_channel`]; } else { module_dma_ch = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_rx_channel`]; } return (module_dma_ch.config.filter(o => o.name === 'PacketsCount'))[0].default; } function getNetifCount(instance) { let driverVer = soc.getDriverVer("enet_cpsw"); let totalNumNetifs = 0; let instances; let module; instances = instance.netifInstance; module = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_lwipif_netif`]; for(let num = 0; num < instances.length; num++) { let num_instance = instances[num]; totalNumNetifs++; } return totalNumNetifs; } function getNetifConfig(instance, InstNum) { let driverVer = soc.getDriverVer("enet_cpsw"); let instances; let module; instances = instance.netifInstance; module = system.modules[`/networking/enet_cpsw/${driverVer}/enet_cpsw_lwipif_netif`]; let cfgArray = new Array(); for(let num = 0; num < instances.length; num++) { let num_instance = instances[num]; let num_config = module.getInstanceConfig(num_instance)[`moduleInstance`]; cfgArray.push(num_config); } return cfgArray[InstNum]; } function getNetifPacketDequeueMode(instance){ let enableTimerBasedPoll = (getNetifConfig(instance, 0).packetDequeueMode === "TimerBasedPolling") ? 1 : 0; return enableTimerBasedPoll; } function verifyNetifPacketDequeueMode(instance){ let timerEnabledNetifcount = 0; let firstNetifMode = getNetifConfig(instance, 0).packetDequeueMode; for (let Idx = 1; Idx < getNetifCount(instance); Idx++) { if(getNetifConfig(instance, Idx).packetDequeueMode !==firstNetifMode){ return false; } } return true; } function getDefaultNetifCount(instance) { let defaultNetifCount = 0; for (let Idx = 0; Idx < getNetifCount(instance); Idx++) { defaultNetifCount += (getNetifConfig(instance, Idx).isDefault === true) ? 1 : 0; } return defaultNetifCount; } function getDefaultNetifIdx(instance) { let defaultNetifIdx = -1; for (let Idx = 0; Idx < getNetifCount(instance); Idx++) { if(getNetifConfig(instance, Idx).isDefault === true) { defaultNetifIdx = Idx; break; } } return defaultNetifIdx; } function getCpuID() { return system.getScript(`/drivers/soc/drivers_${common.getSocName()}`).getCpuID(); } function validate(instance, report) { pktPoolScript.validate(instance, report); aleScript.validate(instance, report); mdioScript.validate(instance, report); macportScript.validate(instance, report); hostportScript.validate(instance, report); if (getNetifCount(instance) > 0) { if (getDefaultNetifCount(instance) !=1) { report.logError(`Only one netif can be set as default`, instance, "netifInstance"); } if(verifyNetifPacketDequeueMode(instance) === false){ report.logError(`Both the Netif should be in same PacketDeque Mode`, instance,); } if (getNetifCount(instance) === 2) { if ((instance.DisableMacPort1 === true) || (instance.DisableMacPort2 === true)) { report.logError("Both MAC ports in MAC PORT Config should be enabled to support two NetIfs", instance); } if ((instance.macOnlyEn_hostPort === false) || (instance.macOnlyEn_macPort1 === false) || (instance.macOnlyEn_macPort2 === false)) { report.logError("All Ports in 'ALE Config -> ALE Port Config -> MAC-only mode config' should be in MAC-only mode in case of two NetIfs", instance); } } } if (/^([0-9a-fA-F]{2}[:-]){5}[0-9a-fA-F]{2}(,([0-9a-fA-F]{2}[:-]){5}[0-9a-fA-F]{2})+/.test(instance.macAddrList) == false) { report.logError(`Invalid macAddrList Entry`, instance, "macAddrList"); } } function moduleInstances(instance) { let Instances = new Array(); let driverVer = soc.getDriverVer("enet_cpsw"); let maxCh = 8; let maxNetif = 2; Instances.push({ name: "txDmaChannel", displayName: "ENET tx dma channel", moduleName: `/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_tx_channel`, useArray: true, minInstanceCount: 1, maxInstanceCount: maxCh, defaultInstanceCount: 1, collapsed:false, group: "cpdmaChConfig", }); Instances.push({ name: "rxDmaChannel", displayName: "ENET rx dma channel", moduleName: `/networking/enet_cpsw/${driverVer}/enet_cpsw_${driverVer}_rx_channel`, useArray: true, minInstanceCount: 1, maxInstanceCount: maxCh, defaultInstanceCount: 1, collapsed:false, group: "cpdmaChConfig", }); Instances.push({ name: "netifInstance", displayName: "NETIF instance", moduleName: `/networking/enet_cpsw/${driverVer}/enet_cpsw_lwipif_netif`, useArray: true, minInstanceCount: 0, maxInstanceCount: maxNetif, defaultInstanceCount: 0, collapsed:false, group: "lwipIfConfig", }); return (Instances); } function addSharedModuleInstances(inst) { let modInstances = new Array(); if((inst.DisableMacPort1 === false) && (inst.customBoardEnable === false)){ modInstances.push({ name: "ethphy1", displayName: "Port 1 PHY Configuration", moduleName: "/board/ethphy_cpsw_icssg/ethphy_cpsw_icssg", requiredArgs: { boardType: inst.BoardType, peripheral: "CPSW_MAC_PORT_1", enableCustomBoard: inst.customBoardEnable, }, group: "macPort1Cfg", }); } if((inst.DisableMacPort2 == false) && (inst.customBoardEnable === false)){ modInstances.push({ name: "ethphy2", displayName: "Port 2 PHY Configuration", moduleName: "/board/ethphy_cpsw_icssg/ethphy_cpsw_icssg", requiredArgs: { boardType: inst.BoardType, peripheral: "CPSW_MAC_PORT_2", enableCustomBoard: inst.customBoardEnable, }, group: "macPort2Cfg", }); } return modInstances; } function getCpuInfo() { const cpuInfo = new Map( [ ['CSL_CORE_ID_R5FSS0_0',{subsystem: "R5FSS", clusternum: "0", core: "0"}], ['CSL_CORE_ID_R5FSS0_1',{subsystem: "R5FSS", clusternum: "0", core: "1"}], ], ); return cpuInfo.get(getCpuID()); } let enet_cpsw_module_name = "/networking/enet_cpsw/enet_cpsw"; let enet_cpsw_module = { displayName: "Enet (CPSW)", longDescription: "Driver for Common Port SWitch (CPSW). Support MAC, Switch and used in auto and industrial Ethernet to run TCP/IP, AVB etc. applications. TSN is supported via CPSW", templates: { "/drivers/pinmux/pinmux_config.c.xdt": { moduleName: enet_cpsw_module_name, }, "/drivers/system/system_config.h.xdt": { driver_config: "/networking/enet_cpsw/templates/enet_cpsw_v3.h.xdt", moduleName: enet_cpsw_module_name, }, "/drivers/system/power_clock_config.c.xdt": { moduleName: enet_cpsw_module_name, }, "/board/board/board_config.h.xdt": { board_config: getBoardConfigTemplateInfo().Header, moduleName: enet_cpsw_module_name, }, "/board/board/board_config.c.xdt": { board_config: getBoardConfigTemplateInfo().Cfile, moduleName: enet_cpsw_module_name, }, "/networking/common/enet_config.c.xdt": { enet_mem_config: "/networking/enet_cpsw/templates/enet_app_memutils_cfg_cpdma.c.xdt", enet_syscfg_info: "/networking/enet_cpsw/templates/enet_app_syscfg_info.c.xdt", moduleName: enet_cpsw_module_name, }, "/networking/common/enet_config.h.xdt": { enet_config: "/networking/enet_cpsw/templates/enet_syscfg.h.xdt", moduleName: enet_cpsw_module_name, }, "/networking/common/enet_open.c.xdt": { enet_open: "/networking/enet_cpsw/templates/enet_init.c.xdt", enet_init_config: "/networking/enet_cpsw/templates/enet_app_cpsw_cfg.c.xdt", moduleName: enet_cpsw_module_name, }, "/networking/common/enet_open.h.xdt": { enet_open: "/networking/enet_cpsw/templates/enet_init.h.xdt", moduleName: enet_cpsw_module_name, }, "/networking/common/enet_soc.c.xdt": { enet_soc: getSocConfigTemplateInfo().Cfile, moduleName: enet_cpsw_module_name, }, "/networking/common/enet_lwipif.c.xdt": { enet_lwipif: "/networking/enet_cpsw/templates/enet_lwipif.c.xdt", moduleName: enet_cpsw_module_name, }, "/networking/common/enet_lwipif.h.xdt": { enet_lwipif: "/networking/enet_cpsw/templates/enet_lwipif.h.xdt", moduleName: enet_cpsw_module_name, }, }, defaultInstanceName: "CONFIG_ENET_CPSW", config: [ { name: "BoardType", description: "Board selection for AM261x", displayName: "BoardType", default: "am261x-lp (dp83tg720 phy)", options: [ { name: "am261x-lp (dp83tg720 phy)", }, { name: "am261x-lp (dp83826 phy)", }, { name: "am261x-som", }, ], }, enet_cpsw_system_config, enet_cpsw_cpdma_channel_config, pktPoolScript.config, enet_cpsw_lwipIf_config, aleScript.config, mdioScript.config, hostportScript.config, macportScript.config, cptsScript.config, enet_cpsw_board_config, pinMuxScript.config, ], moduleStatic: { modules: function(inst) { return [{ name: "system_common", moduleName: "/system_common", }] }, }, moduleInstances: moduleInstances, utils: utilsScript, sharedModuleInstances: addSharedModuleInstances, pinmuxRequirements, getInterfaceNameList, getPeripheralPinNames, getClockEnableIds, getClockFrequencies, getDmaInterface, getInstIdTable, getCpswInstInfo, getBoardConfigTemplateInfo, getCpuID, getCpuInfo, getSocConfigTemplateInfo, getTxPacketsCount, getRxPacketsCount, getRxChannelCount, getTxChannelCount, getNumCpdmaDesc, getChannelConfig, getDefaultPacketCount, getNetifCount, getNetifConfig, getNetifPacketDequeueMode, getDefaultNetifIdx, getMiiConfig, validate: validate, }; exports = enet_cpsw_module;

Regards,
Shaunak

+1 Shaunak Deshpande 3 months ago in reply to Shaunak Deshpande

TI__Genius 16332 points

Adding to the reply above,

1. You also need to update your source/drivers/soc/am261x files with the files below:

8255.soc_rcm.h

8255.soc_rcm.c

Post this, rebuild your libraries in the SDK, then re-build your application. This should fix the incorrect clock.

2. We also have the AM261x v10.02 SDK released with some bug-fixes (including the one above) in case you are interested in checking that out.

Regards,
Shaunak

0 Yang Lingyun 3 months ago in reply to Shaunak Deshpande

Prodigy 50 points

Hi Shaunak,

Sorry for late response cause my PC OS is reinstalled.

I tried the method you suggested and the problem is fixed.

I update soc_rcm.h/c and enet_cpsw_am261x.syscfg.js on mcu_plus_sdk_am261x_10_00_01_10 and rebuild drivers_r5f.

Boot from flash and run code, both rx and tx msgs can be captured by wireshark.

Thank you very much!

Arm-based microcontrollers

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