TMS570LC4357: HET2 and HTU, how to reset HTU when system in idle

Thomas Langholen

Part Number: TMS570LC4357

Tool/software:

We are using TMS570LC4357 HET2 with HTU, dual buffer, configured for 127 frames, each 5 elements.

I want to stop the HET when system is in idle. On external command we then need to start the transfer of data again. It seems to work, and I am using GCR register to start and stop the HET.

The problem is to reset the HTU when in Idle. Reading the CFCOUNT register of the CDCP it picks up where it stopped when we are staring the HET again.

I tried to reset the CFADDRA and CFADDRB and write 0 to CFCOUNT of the CDCP when in idle without any luck.

Any tips?

Also how to stop the HTU when debugging, haven’t figured out how.

When free running and reading the HTU buffers the data looks ok but when I break in the interrupt for the HTU the data looks wrong. Large chunks of 0x00. Each frame has a counter that increases like expected when system is running that we use for verification.

Thnaks.

4 months ago

0 jagadish gundavarapu 3 months ago

TI__Guru 69891 points

Hi Thomas,

Can you try to disable and enable the HTU once and see for restart of the communication.

--
Thanks & regards,
Jagadish.

0 Thomas Langholen 3 months ago in reply to jagadish gundavarapu

Prodigy 20 points

Thank you, I missed that, and it worked in regard to the stopping and "resetting" of HTU.

Also verified by reading CDCP->CFCOUNT

bit 8, DEBM is also 0 but I can see that buffer_a is still being filled with data when I break the debugger, my understanding is that it should have stopped?

My biggest issue now is that it seems that when I get a buffer_b interupt the buffer does not contain valid data, some parts looks ok but most data is 0x00. Buffer_a looks all good and it is consistent.

I have looked at all settings and intervals between interrupts looks correct. When the system is running, and I enable Continuous Refresh in the debugger I can see that both buffers are filled and continuous updated with valid data it’s just that when the interupt for buffer_b triggers it has spots of 0x00. I have also tried to move the buffer in MCU memory to ensure that I don’t have anything else writing over without any luck. I am using HET2 with HTU2

I have also verified that the CFCOUNT for the alternating buffers are counting down to 0 before the interrupts triggers.

What am I missing?

Thanks and regards,

Thomas

Memmory view from interupt:

Memmory view when running and how it should be:

+1 jagadish gundavarapu 3 months ago in reply to Thomas Langholen

TI__Guru 69891 points

Hi Thomas,

As mentioned in below thread, can you disable the cache and see the behavior:

(35) TMDX570LC43HDK: TMDX570LC43HDK Live Expression in CCS - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

--
Thanks & regards,
Jagadish.

0 Thomas Langholen 3 months ago in reply to jagadish gundavarapu

Prodigy 20 points

Hi this solved it, what is the penalty by disable cache?

Thanks & regards,

Thomas

0 jagadish gundavarapu 3 months ago in reply to Thomas Langholen

TI__Guru 69891 points

Hi Thomas,

There won't be any big penalty in disabling the cache. Cache mainly helpful to enhance the performance (speed) for accessing repeat data. I mean if CPU accessing certain part of the data repeatedly in the code, then in that case, cache will be helpful to access the data fast. I mean only first time CPU need to fetch the data from main memory and all the other times it will get data from cache instead of main memory every time.

You no need to do complete cache disable and there is an alternative as well, please refer below thread to find out the alternative method:

(20) TMDX570LC43HDK: DMA can't read some data correctly(trying to sci tx) - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

--
Thanks & Regards,
Jagadish.