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M4 I2C Problem

I have been using the I2C on my M3s with no problems.  I tried to implement the same type of code on my new M4 evaluation code and am having some issues.  One line goes low the the other stays high; both are pulled high to 3.3V via 2.2k resistors.  Here is my code:

 

 

#include <string.h>

#include <stdarg.h>

#include <stdint.h>

#include <stdbool.h>

#include <stdlib.h>

#include <stdio.h>

 

#include "inc/hw_ints.h"

#include "inc/hw_memmap.h"

#include "inc/hw_types.h"

#include "inc/hw_uart.h"

#include "inc/hw_ssi.h"

#include "inc/hw_i2c.h"

 

#include "driverlib/gpio.h"

#include "driverlib/interrupt.h"

#include "driverlib/ssi.h"

#include "driverlib/rom.h"

#include "driverlib/sysctl.h"

#include "driverlib/systick.h"

#include "driverlib/uart.h"

#include "driverlib/udma.h"

#include "driverlib/i2c.h"

#include "driverlib/timer.h"

#include "driverlib/adc.h"

#include "driverlib/fpu.h"

 

#define Tps 10

 

volatile uint32_t Tick;

 

#ifdef DEBUG

void __error__(char *pcFilename, unsigned long ulLine){

}

#endif

 

void I2C0IntHandler(void){

I2CMasterIntClear(I2C0_MASTER_BASE);

}

 

void SysTickHandler(void){

    Tick++;

}

 

int main(void){

FPUEnable();

FPULazyStackingEnable();

 

SysCtlClockSet(SYSCTL_USE_OSC | SYSCTL_SYSDIV_1 | SYSCTL_OSC_INT);

 

    SysTickPeriodSet(ROM_SysCtlClockGet() / Tps);

    SysTickEnable();

    SysTickIntEnable();

 

SysCtlPeripheralEnable(SYSCTL_PERIPH_I2C0);

SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);

GPIOPinConfigure(GPIO_PB2_I2C0SCL);

GPIOPinConfigure(GPIO_PB3_I2C0SDA);

GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);

    I2CMasterInitExpClk(I2C0_MASTER_BASE, SysCtlClockGet(), true);

    I2CMasterIntEnable(I2C0_MASTER_BASE);

IntEnable(INT_I2C0);

IntMasterEnable();

 

while(1){

Tick = 0;

while(Tick < Tps){

}

I2CMasterSlaveAddrSet(I2C0_MASTER_BASE, 0x40, false);

I2CMasterDataPut(I2C0_MASTER_BASE, 0x55);

I2CMasterControl(I2C0_MASTER_BASE, I2C_MASTER_CMD_SINGLE_SEND);

}

}

  • The same exact code (minus the fpu enable code) works great on a 9B92.  Is there some I2C or pin setup that is different in an M4 part?

  • Natan,

    Yes. LM4F introduces high-speed i2c, and the SCL pin must be set to an open drain. Just simply break your GPIOPinTypeI2C call into two, using the newer function GPIOPinTypeI2CSCL to accomplish this:

    GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_2 | GPIO_PIN_3);

    -to-

    GPIOPinTypeI2C(GPIO_PORTB_BASE, GPIO_PIN_3);

    GPIOPinTypeI2CSCL(GPIO_PORTB_BASE, GPIO_PIN_2);

  • That worked thank you.  Is there any document listing of changes required when transitioning from M3 to M4?

  • This change was not brought on because the new core is M4, but because features were added to a peripheral in the micocontroller.  The Stellaris family has gone through a significant evolution over time.

    What's needed is a document (or series of documents) detailing the differences in the different generations of the Stellaris parts.

    Significant differences over time include:

    * Extra controls were added to prevent accidental repurposing of the JTAG pins

    * UART modules have had TX complete interrupt added

    * Pin multiplexing requires additional setup on later generation parts

    * Flash behavior is different in different parts (whether you can write multiple times between erases)

    * I2C functionality has changed requiring different setup code

    And I'm sure there are other things I've forgotten on the list.

    Differences in the part generations and the many different IDEs and development environments supported make it critical to give specifics about what part you are using, what IDE and toolchain are you using, etc. when asking questions about a problem.

     

  • slandrum said:

    This change was not brought on because the new core is M4, but because features were added to a peripheral in the micocontroller.  The Stellaris family has gone through a significant evolution over time.

    You're absolutely right. It is a change to the I2C peripheral.

    And I agree on the need for a comprehensive list of significant differences. There is a recently posted application note on the LM4F product page: Differences Among Stellaris Product Classes (Rev. A). Hopefully this can be a valuable reference.

  • This is a comment from my viewpoint but it may be bothering others as well.

    I spent a couple of hours trying to debug I2C for an LM4F231 and happened to find this thread. I was aware of the note in the user's guide "This function should only be used for Blizzard-class devices." Had I known that the LM4F231 was a member, it might have saved me some trouble. I found NO reference in the user's guide about what "Blizzard-class" meant. In an earlier support thread I raised the question concerning another "class" and got the response that TI was moving away from these classifications. However, here it is again.

    It would help if somewhere obvious (and handy to readers of the User's Guide) the information on what processors fell into each class were handy.

    Thanks

  • This alleged document:

    And I agree on the need for a comprehensive list of significant differences. There is a recently posted application note on the LM4F product page: Differences Among Stellaris Product Classes (Rev. A). Hopefully this can be a valuable reference.

    Appears to have disappeared...