AM263P4-Q1: AM263P4-Q1

Hi Rapeti

• The datasheet's "maximum conversion time of 250ns" likely refers to the fastest achievable total sample time, which corresponds to a 4 MSPS throughput (1 / 250ns = 4 MSPS).
• The "76 System Clock cycles (765ns = 380ns) for t_EOC alone" from Table 7-115 of the manual needs careful interpretation.
  • It's possible this figure refers to the conversion time in ADCCLK cycles, and it was then incorrectly multiplied by the SYSCLK period.
  • I'll have to check with a HW expert and get back to you on this figure.

The most reliable way to understand the timing for a specific sampling rate is to look at working examples and the underlying calculations. The example examples/drivers/adc/adc_soc_continuous/adc_soc_continuous.c is particularly relevant as it targets ~4 MSPS.

According to the comments in examples/drivers/adc/adc_soc_continuous/adc_soc_continuous.c (lines 45-56):

The ADC clock is prescaled by a factor of 3. This means 

• The sampling window (sampleWindow) is 17 SYSCLK cycles.

• The conversion proper (t_conv) takes 31 SYSCLK cycles for this specific prescaler setting.

• The total time for one SOC (Start of Conversion) is stated as 49 SYSCLK cycles (17 S+H + 31 Conv = 48 SYSCLKs; the 49 might include a small overhead or be a rounded figure).

as we have SYSCLK of 200 MHz (5 ns period):

Total time = 48 5 ns = 240 ns.

Sampling Rate = 1 / 240 ns = ~4.17 MSPS.

This aligns well with the 4 MSPS target and the datasheet's 250ns capability.

So, for the prescaler setting of ADC_CLK_DIV_3_0, the effective conversion proper time is 31 SYSCLK cycles.

Rapeti Sravanthi said:

Could you please explain how to set ADC for 4msps, 3msps, 2msps.

To Achieve 4 MSPS (Target Total Time: 1 / 4MHz = 250 ns):

Reasoning:

• Total SYSCLKs needed: 250 ns / 5 ns/SYSCLK = 50 SYSCLKs.
• sampleWindow = Total SYSCLKs - Conversion Proper SYSCLKs = 50 - 31 = 19 SYSCLKs.
• Using sampleWindow = 17 (as in adc_soc_continuous.c) gives: 17 (S+H) + 31 (Conv) = 48 SYSCLKs = 240 ns (~4.17 MSPS). This is a practical value.

Configuration:

• Adc Prescaler: 3
• Sample Window: 17 SYSCLK cycles

To Achieve 3 MSPS (Target Total Time: 1 / 3MHz = ~333.33 ns):

Reasoning:

• Total SYSCLKs needed: 333.33 ns / 5 ns/SYSCLK = ~66.67 SYSCLKs.
• sampleWindow = 66.67 - 31 = ~35.67 SYSCLKs. Choose sampleWindow = 35.
• Total: 35 (S+H) + 31 (Conv) = 66 SYSCLKs = 330 ns (~3.03 MSPS).

Configuration:

• Adc Prescaler: 3
• Sample Window: 35 SYSCLK cycles

Let me know if this helps!

Regards,
Akshit