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AM2432: GPIO Pin PLL Control

Part Number: AM2432

Tool/software:

I need to evaluate Sitara AM2432 GPIO pin's 800MHz signal that is committed in datasheet.

My understanding is to use PLL to turn the 25MHz reference clock to generate the high speed output.

It is hard to find the API functions in manual to control PLL.

And there is no good example code in SDK example library.

Can you please suggest me the procedure and share the APIs to implement this function.

Additionally, if I need to further divide the 800MHz signal to specific frequence for other functions, please share procedure if available.

Thanks.

Thanks & Best regards

Hao (Wang hao)

  • Hi Hao,

    I need to evaluate Sitara AM2432 GPIO pin's 800MHz signal that is committed in datasheet.

    Can you please provide a screenshot, which section of datasheet are you referring to?

    Can you please suggest me the procedure and share the APIs to implement this function.

    You can check all the PLL setting via clock tree tool. Please refer Clock Tree AM64x for details. The tool uses AM64x devices, the same settings will be applicable for AM243x also.(Excluding A53 cores setting, if any).

    My understanding is to use PLL to turn the 25MHz reference clock to generate the high speed output.

    You are not supposed to change the PLL setting as this PLL are connected to different IPs and will affect the overall system performance.

    Regards,

    Tushar

  • Tushar

    Thanks for responses.

    Can you please suggest how to access the Clock Tree Tool from CCS?

    How to integrate the settings to my program?

    Please recommend if there is manual for it.

    Thanks.

    Thanks & Best regards

    Hao (Wang hao)

  • Hello Hao,

    Can you please suggest how to access the Clock Tree Tool from CCS?

    Clock Tree tool is only available as web version. So from CCS you can not visualize clock tree.

    How to integrate the settings to my program?

    You can visualize the clock setting in the tool and configure the value in register as shown in the clock tree tool.

    Regards,

    Tushar

  • Tushar

    Thanks for answers.

    Can you please instruct how to import PLL setting to CCS program and configure the register value?

    If I generate the clock by TIMER function, how to connect the setting to GPIO channel in syscfg?

    Please share inputs.

    Thanks.

    Thanks & Best regards

    Hao (Wang hao)

  • Hi Hao,

    Can you please instruct how to import PLL setting to CCS program and configure the register value?

    The output from the clock tree tool can not be imported to CCS. The values needs to be modified manually in the application.

    If I generate the clock by TIMER function, how to connect the setting to GPIO channel in syscfg?

     Can you please specify the above use case? What is meant by connecting GPIO channel in syscfg?

    For example, if I want to change the Timer0 clock, I need to modify the PLL_HSDIV_A output to generate different frequency.

    This can be done by modifying HSDIV value in PLL0_HSDIV_CTRL0 Register at address 0x680080.

    Please refer the below image.

    Be cautious while you change any PLL, as this are connected to various other IPs and will impact the overall system performance.

    Hope the above information helps.

    Regards,

    Tushar

  • Tushar

    I will generate clock on GPIO channels.

    My understanding is that PLL is internal resource that provide reference clock to Timer by physical route.

    But as fresher, I am not sure if PLL can be routed to any GPIO channel to give specified clocks (e.g. 100KHz, 1MHz).

    Can you please suggest good approach to create clock on GPIO channel?

    If we have to utilize Timer, do we need to use interrupt?

    Please share advise.

    Thanks.

    Thanks & Best regards

    Hao (Wang hao)

  • Hi Hao,

    My understanding is that PLL is internal resource that provide reference clock to Timer by physical route.

    Yes, the above understanding is correct.

    But as fresher, I am not sure if PLL can be routed to any GPIO channel to give specified clocks (e.g. 100KHz, 1MHz).

    The GPIO module is connected to the PLL0_HSDIV_A and a divider which feeds 125 MHz frequency to the GPIO module. 

    Please refer below image.

    Regards,

    Tushar