• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 30 subscribers
  • Views 254 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

TPS7H4010-SEP: BIAS Pin Configuration for Sequential Powering with TPS7H4010-SEP

Dhir Gandhi
Prodigy 200 points
Part Number: TPS7H4010-SEP


Tool/software:

Hello,

I plan to use two TPS7H4010-SEP devices in a sequential powering configuration. The first IC will have Vout = 1.2V, and its PGood output will be connected to the EN pin of the second IC, which has Vout = 3.3V.

According to the datasheet, the BIAS pin can be tied to a 3.3V or 5V power rail to improve efficiency. My question is: Can I connect the BIAS pin of the 1.2V IC to the 3.3V rail, even though the 3.3V IC will power on only after the 1.2V IC?

  • 0
    TI__Expert 5801 points

    Hi Dhir,

    While I do not think we have tested this specific implementation, the TPS7H4010-SEP automatically switches over from using PVIN to BIAS as the VCC LDO source when BIAS rises above the VBIAS_ON threshold.

    Your proposed set-up is conceptually very similar to connecting BIAS to the device's own VOUT when VOUT=3.3V, In that there is a switchover of the VCC LDO source some time after startup. Since this is a supported configuration, I have little concern with your proposed implementation.

    Thanks,

    Andy

  • 0 in reply to Andy Fondaw
    Prodigy 200 points

    Thanks for clarifying Andy!

    Would it be possible to perform simulation to verify this functionality?

  • 0 in reply to Dhir Gandhi
    TI__Expert 5801 points

    Hi Dhir,

    I am running a simulation now. It may take a little while for it to finish, but I will post another reply with the results when it is done.

    Thanks,

    Andy

  • +1 in reply to Andy Fondaw
    TI__Expert 5801 points

    Hi Dhir,

    The Simulation finished with everything looking okay. Please find a screenshot of the results below:

    The enable of the 3.3V rail was connected to the PGOOD of the 3.3V rail, and the BIAS pin of the 1.8V rail was connected to VOUT of the 3.3V rail.

    If you would like to explore further simulations yourself, the TPS7H4010-SEP PSPICE model is available here on ti.com.

    Thanks,

    Andy

  • 0 in reply to Andy Fondaw
    Prodigy 200 points

    Thanks Andy!

  • 0 in reply to Dhir Gandhi
    Prodigy 200 points

    Hello Andy,

    Andy Fondaw said:
    The enable of the 3.3V rail was connected to the PGOOD of the 3.3V rail

    Is this a typo? The enable pin of 3.3V should be connected to PGOOD of 1.8V rail.

    Also, can you let me know why is there a 0.2 ms difference in the startup of 3.3V after powering on the 1.8V ic?

  • +1 in reply to Dhir Gandhi
    TI__Expert 5801 points

    Hi Dhir,

    Yes, that was a typo. The EN pin of the 3.3V was connected to the PGOOD of tghe 1.8V rail.

    As for the delay, that is caused by the deglitch delay between the output voltage of the regulator being good, and the rising edge of the PGOOD signal. PGOOD_RISE in the datasheet (PGOOD rising edge deglitch delay).

    The 3.3V regulator started up when the 1.8V PGOOD went high, but the simulation uses the Max value for the PGOOD rising edge delay (200us)

    Output voltages are only shown in the simulation plot, not the PGOOD signal.

    Thanks,

    Andy