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Original question:

MCU-PLUS-SDK-AM243X: Enet(CPSW) can not be used with PRU(ICSS)

MCU-PLUS-SDK-AM243X: Multiple Ethernet Peripheral Configuration Issue (CPSW and ICSSG)

Zachary Lutz
Prodigy 20 points
Part Number: MCU-PLUS-SDK-AM243X
Other Parts Discussed in Thread: SYSCONFIG

Tool/software:

Product: MCU+ SDK AM243x (Version 10.00.00.20)
Tool: SysConfig (Version 1.20.0+3587)

Issue Description:
When configuring both CPSW and ICSSG Ethernet peripherals in SysConfig, the tool generates duplicate macro definitions in the configuration files, causing compiler warnings and potential runtime issues. This is a critical issue as the AM243x EVM has both Ethernet peripherals physically present and they should be usable simultaneously.

Hardware Context:
- AM243x EVM with both CPSW and ICSSG Ethernet ports

Steps to Reproduce:
1. Open a project in SysConfig
2. Add both CPSW and ICSSG Ethernet peripherals
3. Configure each peripheral with appropriate settings
4. Generate the configuration files
5. Build the project

Expected Behavior:
- SysConfig should generate properly namespaced or conditionally compiled configurations for each peripheral
- No macro redefinition warnings should occur
- Both peripherals should be able to operate simultaneously
- This is a valid use case that should be supported by the tool

Actual Behavior:
- The tool generates duplicate macro definitions in ti_enet_config.h and ti_enet_config.c
- Compiler warnings about macro redefinitions occur
- Example redefinitions:
- ENET_SYSCFG_MAX_MAC_PORTS (2U vs 1U)
- ENET_SYSCFG_ENABLE_MDIO_MANUALMODE (1U vs 0U)
- ENET_SYSCFG_NETIF_COUNT (1U vs 0U)
- ENET_SYSCFG_DEFAULT_NETIF_IDX

Impact:
- Compiler warnings that need to be suppressed
- Potential runtime issues due to conflicting configurations
- No viable workaround exists as the files are auto-generated
- Users cannot use both Ethernet peripherals simultaneously as intended

Additional Information:
- The issue appears to be in the code generation logic of SysConfig
- The tool should either:
1. Generate separate configuration files for each peripheral type
2. Use different macro namespaces for each peripheral
3. Use conditional compilation to separate the configurations

  • 0
    TI__Mastermind 27300 points

    Hi Zachary Lutz,

    Thanks for your query.

    Please refer below documentation and let me know if you have any further query.

    Five Ethernet Port Enablement on AM64x and AM243x

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 20 points

    Hi Ashwani,

    Thank you for the prompt reply. I have a few questions regarding the application note:

    1. What is the "SEM board" that is meant to be connected via HSE connector?
      1. Do I strictly need this to run CPSW & ICSSG Ethernet, or is this necessary for enabling all 5 ethernet ports?
      2. Suppose I only care about ICSSG1 and CPSW (and NOT ICSSG0, for example) 
    2. How can I procure the "SEM board" connected over HSE connector?
      1. I see that this same question has been asked in E2E forum, can you provide any further insight on how to procure this board?
    3. This application note uses AM64x-EVM as an example. Is this implementation applicable for the AM243-EVM as well?
      1. Is the "SBL update" section relevant for AM243x?

    Thanks again,

    Zach

  • 0 in reply to Zachary Lutz
    TI__Mastermind 27300 points
    Zachary Lutz said:
    What is the "SEM board" that is meant to be connected via HSE connector?

    This is TI-Internal board (NOT ORDERABLE) connected at HSE port to evaluate ICSSG0.

    You can connect with TI-Marketing (AM64x) team for more info on this.

    Zachary Lutz said:
    This application note uses AM64x-EVM as an example. Is this implementation applicable for the AM243-EVM as well?

    Difference is: AM243x does not have A53 core. 

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    Prodigy 20 points
    Ashwani Goel said:
    You can connect with TI-Marketing (AM64x) team for more info on this.

    How can I connect with TI-Marketing team? 

    Ashwani Goel said:
    Difference is: AM243x does not have A53 core. 

    Understood, is it possible to run the example from the R5 cores? or M4/R5 core combination?

  • 0 in reply to Zachary Lutz
    TI__Mastermind 27300 points

    I forwarded your query to marketing team.

    Please allow some time to get you back.

    Regards

    Ashwani

  • 0 in reply to Ashwani Goel
    TI__Expert 3115 points

    Hi Zachary,

    What questions do you have on the 5-port AM64x/AM243x support?  What is type of application are you working on?

    Best regards,

    Mike

  • 0 in reply to Michael Firth
    Prodigy 20 points
    Michael Firth said:
    What questions do you have on the 5-port AM64x/AM243x support?

    It appears that the application note regarding 5 ethernet port enablement on AM64x/AM243x suggests using one core per ethernet peripheral, and using shared memory to link the cores. The example is implemented on AM64x-EVM, is it possible to realize this on the AM243x-EVM?

    I understand the SEM card is for providing the 4th and 5th ethernet ports for ICSSG0. Can the example run without this expansion card? 

    Is it possible drive both Enet peripherals from a single core? Or is it necessary to use multiple cores for multiple Enet peripherals?

    If it is possible to drive both ICCSG and CPSW Enet from a single core, do you have a working example to share? 

    Michael Firth said:
    What is type of application are you working on?

    I am running an EtherCAT master stack on one core for a power conversion application. This EtherCAT master uses the ICSSG1 Ethernet peripheral. I also need to run an MQTT client over the CPSW Ethernet peripheral. When I attempt to bring in CPSW through sysconfig, the generated code for each Ethernet peripheral is self-conflicting. Several macros and functions are duplicated. Cannot compile. 

  • 0 in reply to Zachary Lutz
    TI__Mastermind 27050 points

    Trying to simplify this, you just need 2x Ethernet. One port from ICSSG for EtherCAT master (I'm assuming you have a stack from Acontis or IBV or your own). Second port from CPSW. So no need to discuss extension boards, https://www.ti.com/tool/TMDS243EVM has 3 Ethernet ports. Or do you need the extra ports or access to ICSSG0 ?

    The MCU+ and sysconfig might have limitations with multiple instances of Ethernet in parallel that are fixed or in the process of being fixed. First I'd recommend moving to the latest (11.00.00.15 is at https://www.ti.com/tool/download/MCU-PLUS-SDK-AM243X ) and seeing if the issue is still there.

      Pekka

  • 0 in reply to Ashwani Goel
    Prodigy 20 points
    Hi Ashwani + team,
    I have received the TI AM64x-EVM board and have been trying to work through the example in the 5 port ethernet application note. Things become a bit unclear around chapter 1.5.2.1 Resource Allocation - AM64x. I can see that steps 1 through 4 are about de-allocating resources to the Cortex A53 core. Essentially, after running the command gmake -s -C tools/sysfw/boardcfg configure SOC=am64x, SysConfig launches and we set all the TX/RX channels for ICSSG0, ICSSG1, and CPSW Enet peripherals to 0. This much is clear.
    In step 5 and afterwards, things are less clear.
    As you can see, step 5 is a sentence fragment. From what I can make of it this is suggesting that I allocate the CPSW-related packet DMA for TX/RX channel to core MAIN_0_R5_1...is this correct? 
    • Or should I reallocate all CPSW/ICSSG0/ICSSG1 packet DMA for TX/RX channels as well as packet DMA rings for same?
    • For example, should I make packet DMA for ICSSG0 Tx channels set to 8, as it was in the A53_2 settings? 
    • What about the packet DMA ring accelerators? 
    • Below is the resource sharing conflict if I leave Packet DMA ring accelerators for CPSW Tx/Rx channel count as '0'.
    In step 6, it is not made clear if all remaining/existing resource sharing instances of A53_2->MAIN_0_R5_1 should be changed to MAIN_0_R5_1->MAIN_0_R5_3. 
    • For example, if we did not add packet DMA or packet DMA ring accelerators for ICSSG, we would have extraneous rultes for ressource sharing.
    • i.e. what should be done with "Packet DMA Rings for ICSSG1 Tx channel" shared A53_2->MAIN_0_R5_1?
      • Delete?
      • Set "Rings for ICSSG1 Tx channel Count" to 8 (as it was in A53_2), then change resource sharing MAIN_0_R5_1->MAIN_0_R5_3?
    In step 9, it looks like it has me modifying the file named in step 8...is this correct? 
    • If so, I thought I already made such changes in SysConfig, then regenerated files in step 7 based on those changes.
    • If the instructions are to modify the generated code, what lines should be modified? The instructions are not clear
    Overall, the intent of the resource allocation section is not clear. What is the goal? What are the potential pitfalls. I have not used this 
    Thanks,
    Zach