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LP-MSPM0G3507: ADC Repeated Sequence with DMA

Shehab Abdelmagid
Prodigy 120 points
Part Number: LP-MSPM0G3507


Tool/software:

Hello TI,

I have ADC unit with 3 channels in sequence, triggered periodically by HW.

i need DMA to copy conversion results from ADC to uint16_t software buffers immediately after the third channel conversion is done and for this sequence to keep repeating, so that reading each buffer index corresponds to the channel latest data.

What should be my DMA Samples count , Transfer size and DMA trigger configurations in ADC using syscfg and can you explain these parameters in more clear way than the TRM?

Regards,

  • +1
    TI__Mastermind 21867 points

    Hi, one thing need to notice,

    since DMA access ADC FIFO width is 32bit, two ADC result will be copied together to RAM.

    You are using 3 channels, I recommend you to set 4 ADC MEM, to fit DMA 32bit access port.

    MEM0 -> Channel0, MEM1 -> Channel1, MEM2 -> Channel 2, MEM3 -> Channel2.

    MEM3 result will be ignored.

    Once DMA size is down count to 0, DAM Done interrupt will be triggered.

    Here is the code example:

    adc12_sequence_DMA_G3507.zip

  • 0 in reply to Helic Chi
    Prodigy 120 points

    Hi , Thank you for your response, but now if i have 5 channels do i need  to create 3 dummy channels or is there another work around? 

    Side note: for my use case, i don't need to have multiple readings stored in the buffer i just need the latest, so for the 3 channels i used transfer size of 2.

    Also timing is important for me so i think for the 3 channels scenario i have to make the trigger at MEM3 && MEM7&& MEM11 to get fresh samples at every trigger.

    What will be the case for the 5 channels?

  • +1 in reply to Shehab Abdelmagid
    TI__Mastermind 21867 points
    Shehab Abdelmagid said:
    if i have 5 channels do i need  to create 3 dummy channels or is there another work around? 

    5 channel, need to add ADCMEM0~5 is OK, once you are using MEM5 as DAM trigger source, DMA need transfer 3 times with 1 trigger.

    Shehab Abdelmagid said:
    i don't need to have multiple readings stored in the buffer i just need the latest, so for the 3 channels i used transfer size of 2.

    DAM size need to set to 3, but there is no need to do such job.

    Because you can directly read ADC MEM result register when you need.

    You can config ADC in sequence repeat mode, and ADC will update result MEM automatically.

    All you need is to read ADC result MEM 0 ~ 2 for 3 result.

    If you are using DMA and set size to 3, you need to re-enable DMA each time when DMA done.

    The thing you need to handle in ADC DMA is re-enable DMA, re-set des address, re-set size, these steps is slower than directly read result from ADC mem.

  • 0 in reply to Helic Chi
    Prodigy 120 points

    I agree DMA will not add much increase in performance for my use case. but i just wanted to confirm that i need to add like padding channels to keep the copied data consistent in the same place in buffer. Thank you.