Tool/software:
Hi Shaunak,
I want to use 2 core for IPC and we need lock step feature enable also So please let me know how we can enable lockstep and IPC for my project
core implementation as shown below
2. whats the purpose of Cortex m4_0 if it has 4 cores ony
Hi Rohal.
I want to use 2 core for IPC and we need lock step feature enable also So please let me know how we can enable lockstep and IPC for my project
You can switch between lockstep and dual-core mode from the example.syscfg of your SBL application. Suppose you use SBL-QSPI to flash your application, then in the "Bootloader" section, you can choose the R5F Cluster configuration, in this case, both clusters will be in Lockstep mode.
Re-build the SBL before using this SBL's tiimage to flash an application
ALTERNATIVELY, you can also configure this through GEL scripts (with DEV Boot mode), refer this FAQ for the GEL part, (for the SBL part, follow the steps above since we have the option to choose the mode from syscfg now)
2. whats the purpose of Cortex m4_0 if it has 4 cores ony
The M4 Core is dedicated for security related functionalities (Hardware security Manager or the HSM). The M4 core cannot be used directly for running user applications. M4 core is used from the initial ROM bootloader till the application run-time security as well as other security offerings.
Other than this, for user applications, there are 2 PRU cores (part of one PRU-ICSS instance) and 4 R5F cores.
Regards,
Shaunak
