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The signal MOSI in Osc is abnormal.

It should be a logic signal, not a analog signal.

Could you please test SPI with all SPI pin float? and try to catch the signal.

And Q status of POCI in TRM is in CS low but without CLK, POCI will be in Q status.

This is not possible, as there is a hard-wired weak-pullup inside of TLIN14313.

But shouldnt make a difference.

Datasheet says, MOSI will be forced LOW (by MCU). This means a weak-pull-up on SBC shouldnt make any difference, right?

POCI is only controlled by SBC, no pull-resistor attached at all.

That's normal i think, since there is a 240k pullup in SBC, the signal is more reasonable.

Let me check TRM firstly.

Back here.

Benjamin Steiner said:

POCI (MISO) should be undefined (Q-state) and PICO(MOSI) would be forced LOW, while in IDLE.

Correct.

Benjamin Steiner said:

MOSI is kind of floating against 2.8V (like undefined) and MISO is forced LOW.

MISO is blue, and MOSI is red?

It's abnormal.

since MOSI is master/controller output, MSPM0 will keep output a not floating signal to SPI bus.

I think there are influences from TLIN's pullup resistor marked by you, pin 6.

Could you please what will happen when you disconnect M0 and TLIN, try to monitor the SPI signal?

Below is normal the waveform of MOSI during one communication when the slave side has no pull-up resistor :

Below is abnormal the waveform of MOSI during one communication when the slave side has a pull-up resistor(2.2k). 

Comparative analysis reveals a distinct charging process. If the slave side has a pull-up resistor(240k), there will have a more lower charging process, which aligns with the phenomenon you're observing.

Datasheet says, the POCI (MOSI) would be forced Low while in Idle.

Also in your picture the signal goes High.

Is the datasheet wrong?

figure 1 is the normal one.

In figure 2, this is abnormal, there is a pullup resistor connect to POCI.

Below text is the figure description:

Below is abnormal the waveform of MOSI during one communication when the slave side has a pull-up resistor(2.2k). 

Comparative analysis reveals a distinct charging process. If the slave side has a pull-up resistor(240k), there will have a more lower charging process, which aligns with the phenomenon you're observing.

Benjamin Steiner said:

Datasheet says, the POCI (MOSI) would be forced Low while in Idle.

Any page number or datasheet link?

Its page 1247 of SLAU847D. technical reference manual.

Of course i mean PICO (MOSI).

Could you please update to E version, I don't have a d version.

But I got your position, P1306 in TRM, 

• The transmit data line PICO is forced low

Benjamin Steiner said:

Datasheet says, the POCI (MOSI) would be forced Low while in Idle.

Also in your picture the signal goes High.

Is the datasheet wrong?

Seems test result is correct.

There are some gap between TRM and test result, need to confirm this internally.

And pullup resistor will influence the POCI idle status.

Also, at the same time, this high voltage won't influence the SPI communication, you can ignore it, since CLK and CS is not in active status.