MSPM0G3507: MCU SPI (slave) sending data but FIFO is empty ?

Please refer to this part in TRM:

https://www.ti.com/lit/ug/slau846b/slau846b.pdf

19.2.2.5 FIFO Operation Transmit FIFO

And you can fill the peripehral TXFIFO before SPI transfer, make sure if there is no valid SPI data, the data you send is 0x00.

And do you use CS to control each SPI peripheral enable or disable? I think by using CS, it's more easy to handle POCI, by add more Tx handling function in M0 in each SPI stage.

Yes I have already read that....

I fill the FIFO:

When controller send data to target, target will also send back data to controller, this is normal SPI workflow.

So if you want to keep MISO low during controller send data, you can fill target fifo with 0x00 firstly.

That is exactly what I have done above.

I see there are some 0x00 send out from MSPM0, and do you want all sclk that coming into MSPM0 and M0's SPI output pin keeps low during receive data?

Maybe you need check TXFIFO status, if it's empty, you need continue fill TXFIFO with 0x00.

That does not seem to make sense.

If I fill the FIFO with all zeros - which is what I do - then when the FIFO is empty I would expect it to send the last byte in the FIFO.

It should not send some random value.

I think the PACKEN option is non-functional. I'm not quite sure (I haven't tried it) what happens if you set it:

https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/1412230/mspm0g3507-spi-controller-to-transmit-18bit-spi-frame

I vaguely recall that when the FIFO is empty it cycles through the FIFO memory.

Thanks Bruce...the FIFO operation as you describe makes sense; so if I fill it with all zeros *once* then it should also squirt out all zeros all the time.

I will try filling a different way.