Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello TI support, we are currently implementing multipartition bootloader https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/latest/exports/docs/api_guide_am243x/EXAMPLES_DRIVERS_SBL_OSPI_MULTI_PARTITION.html as in IPC ECHO demo, to load and start two R5F cores of our application on the AM2434 SoC (cores r5fss0_0 and r5fss0_1).
Below is the situation and the challenges we are facing:
- On Core 0 (r5fss0_0):
- Ethernet IP is being handled.
- Due to the large memory requirement of the Ethernet IP stack, we have made modifications to the secondary bootloader (SBL) and CCS sysconfig file:
- Configured SBL to specifically boot only these two R5F cores (r5fss0_0 and r5fss0_1), no system file.
- Modified the MSRAM offsets for memory allocation.
- After building and flashing the project into the QSPI:
- The bootloader successfully detects both R5F cores.
- The bootloader successfully copies the binaries for both cores into the MSRAM.
Issue:
Despite the bootloader successfully copying the binaries into MSRAM, neither of the programs on r5fss0_0 nor r5fss0_1 starts execution.
We are seeking clarification and guidance on the following:
- MSRAM Memory Address Allocation:
- Could you confirm which MSRAM addresses can be safely used for loading our binaries?
- Our intention is to handle the Ethernet IP stack on Core 0 (r5fss0_0), and run our firmware on Core 1 (r5fss0_1).
- Procedure for Correct Booting:
- Could there be a specific procedure or sequence required to ensure both cores start running correctly?
- Is there anything additional we need to modify, either:
- In Code Composer Studio (sysconfig settings, linker settings, project settings),
- Or within the SBL program, to facilitate accurate booting and execution of both cores?
We would greatly appreciate detailed input and guidance to overcome these challenges. Thank you in advance for your support.
