MSPM0G3507: Managing RX FIFO and SPI RX DMA

I should add that boxer I POLL I try to disable all SPI DMA activity:

Some observations:

1) The TRM doesn't say, but I expect that the frame is not clocked out directly from the FIFO, but rather from a shift register in the "Transmit/Receive Logic" [Ref TRM Fig 19-1]. That would imply that the FIFO goes empty pretty much immediately after writing the first (only) POLL-ack frame; this probably isn't visible for a Master, since the clocks start immediately, but there could be a noticeable delay for a Slave as it waits for the Master to send some SCKs. A premature FIFO-empty indication could mean you'd see the second POLL after emptying the Rx FIFO.

You might do better with something like DL_SPI_isBusy() rather than  DL_SPI_isTXFIFOEmpty() [Ref TRM Table 19-61, where BUSY also includes FIFO-not-empty].

2) Looking at your trace, it seems as though your Analyzer is at the edge of its resolution, since not all the SCKs are visible individually. If I squint just right, the "glitch" you mention could look rather like another POLL frame.

Does your Analyzer have more channels? /CS and MISO (to see exactly when the POLL-ack is delivered) might be informative. Alternatively, maybe have the POLL word cycle over 0x8000-0x800F or something.

[Edit: If your Slave is using 4-wire (/CS) mode, it seems like "cheap insurance" against glitches to set CTL0:CSCLR=1 (DL_SPI_enablePeripheralAlignDataOnChipSelect()) [Ref TRM Sec 19.2.2.1.1 ].]