Tool/software:
I am trying to verify the R5F core clock configuration on the AM263Px using GEL scripts. My objective is to switch between 400 MHz and 200 MHz clock configurations and verify them using the CycleCounterP_getCount32() API inside periodic RTI ISRs.
I used GEL scripts to configure the R5 clock:
-
For 400 MHz configuration, the register
CFG0_R5SS0_CLK_DIV_SELis set to0x0. -
For 200 MHz configuration, the same register is set to
0x1.
I confirmed these settings by reading the CFG0_R5SS0_CLK_DIV_SEL register after applying the GEL scripts.
I used the CycleCounterP_getCount32() 
API inside the RTI interrupt service routines to measure cycle counts under both configurations.
| Test Case | RTI Period | Clock Config | API Used |
|---|---|---|---|
| TC_01 | 1 ms | 400 MHz | CycleCounterP_getCount32() |
| TC_02 | 1 sec | 400 MHz | CycleCounterP_getCount32() |
| TC_03 | 1 ms | 200 MHz | CycleCounterP_getCount32() |
| TC_04 | 1 sec | 200 MHz | CycleCounterP_getCount32() |
Despite changing the clock divider (0x0 vs. 0x1), the cycle count observed in both configurations remains the same.Attached the observations.
