AM263P4: Multicore microcontroller operation

Hi,

On AM263P4, you have four R5F cores, which can be controlled independently, as well as configured to synchronize and communicate with each other (in all combinations).

For Synchronization and Communication, we use IPC (Inter Processor Communication), You can read the TRM chapter 8 to understand IPC Spinlock and Mailbox and read about Shared memories and interrupts from the TRM.

In software side, you can see the IPC examples in the MCU_PLUS_SDK in the following path: mcu_plus_sdk/examples/drives/ipc and understand how sample multi-core applications work. Let me know if you have any specific questions about Multi-core

Regards,
Shaunak

user5093781 said:

If the answer to the above question is yes, Is it possible to exchange data using memory in each core?

For exsample, CPU0⇔CPU1, CPU0⇔CPU2, CPU0⇔CPU3, CPU0⇔CPU4, CPU1⇔CPU2, CPU1⇔CPU3, CPU1⇔CPU4, CPU2⇔CPU3, CPU2⇔CPU4, CPU3⇔CPU4.

This is how a sample message exchange between cores looks like;

The following sequence is followed for performing a mailbox communication.

1. R5SS0_CORE0 writes the message in appropriate shared SRAM (Eg: MBOX_SRAM).
2. R5SS0_CORE0 interrupt to R5SS1_CORE1 by writing 1 to R5SS0_CORE0_MBOX_WRITE_DONE.PROC3.
3. R5SS1_CORE1 gets the interrupt MBOX_READ_REQ. R5SS1_CORE1 reads the register R5SS1_CORE1_MBOX_READ_REQ. and sees the bit PROC0 is 0x1.
4. R5SS1_CORE1 writes to 0x1 to R5SS1_CORE1_MBOX_READ_REQ.PROC0 .
5. R5SS1_CORE1 reads the message.
6. R5SS1_CORE1 writes 0x1 to R5SS1_CORE1_MBOX_READ_DONE_ACK.PROC0 to generate an acknowledgment interrupt to R5SS0_CORE0 .
7. R5SS0_CORE0 gets the interrupt MBOX_READ_DONE. R5SS0_CORE0 reads the register R5SS1_CORE1_MBOX_READ_DONE and sees bit PROC3 is 0x1.
8. R5SS0_CORE0 writes 0x1 to R5SS1_CORE1_MBOX_READ_DONE. PROC3 to clear the interrupt.

This is how core synchronization using IPC-Spinlock works: