Part Number: AM2434
Tool/software:
Hello experts,
We are currently developing a multicore application for the Sitara AM2434.
Due to hardware space constraints, we are using the smaller package variant without external DRAM. Since, to the best of my knowledge, the controller does not support code execution directly from flash, all code and data for each core must reside within the 2MB of on-chip SRAM.
This makes RAM usage a critical concern for us.
We’ve observed that each R5 core builds and loads its own separate binary, resulting in multiple copies of identical code being stored in memory. A typical example is the printf() function, which is included in each core’s image.
Is there any support from TI for sharing code segments across cores to avoid such redundancy? From a high-level perspective, it seems feasible for a global linker or build system to detect and consolidate shared code.
The “single image” approach described in this document appears to suggest something along those lines:
https://www.ti.com/lit/an/sprab27b/sprab27b.pdf?ts=1749582866208
I would greatly appreciate any insights or recommendations from the TI development team on this topic.
Best regards,
Stefan