LP-AM261: OSPI PHY tuning - OSPI_phyTuneDDR

Tool/software:

Hi All,

I have the LP-AM261 evaluation board, and I am trying to configure the OSPI peripheral to work in DDR 8D-8D-8D mode above 25 MHz.

The flash that was assembled is IS25WX256.

Currently, I managed to make it work in DDR 8D-8D-8D mode, but at 166/8 = 20.75 MHz.

Now I am trying to tune the PHY with the OSPI_phyTuneDDR function, but the code is stuck in the OSPI_lld_phyResyncDLL function at:

/* Wait DLL lock done */
while ((CSL_REG32_FEXT(&pReg->DLL_OBSERVABLE_LOWER_REG,
OSPI_FLASH_CFG_DLL_OBSERVABLE_LOWER_REG_DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD) == 0U))
{

}

As I understand it waits for DQS to be toggled.

Now for the question :

1. Do I need to set the flash to calibration mode, to send data continuously, and generate the DQS signal before I call the OSPI_phyTuneDDR function?

2. Is there an example code for such 8D-8D-8D DDR PHY tuning? (I need at least a frequency of 80 MHz in my application)

Adding my code:

void ospi_flash_diag_lld(void *args)
{
int32_t status = SystemP_SUCCESS;
uint32_t manfId, deviceId;

unsigned char ucFlashStatusReg;
unsigned char ucArr[256];
unsigned char ucFlashWriteReg;
OSPI_ReadCmdParams rdParams1;
OSPI_WriteCmdParams wrParams1;

//volatile unsigned long ulMem;

/* Open OSPI Driver, among others */
Drivers_open();

OSPI_lld_configResetPin(gOspiHandle,2);

DebugP_log("[OSPI Flash Diagnostic Test] Starting ...\r\n");

/* Set Read/Write/Erase */
OSPI_lld_norFlashSetCmds(0x0C, 0x12, 0xD8);

/* Initialize the flash device in 1s1s1s mode */
OSPI_lld_norFlashInit1s1s1s(gOspiHandle);

/* Read ID */
status = OSPI_lld_norFlashReadId(gOspiHandle, &manfId, &deviceId);

if(SystemP_SUCCESS == status)
{
DebugP_log("[OSPI Flash Diagnostic Test] Flash Manufacturer ID : 0x%X\r\n", manfId);
DebugP_log("[OSPI Flash Diagnostic Test] Flash Device ID : 0x%X\r\n", deviceId);
}

ClockP_usleep(2000);

/* Read flash status register */
OSPI_ReadCmdParams_init(&rdParams1);
rdParams1.cmd = 0x70;
rdParams1.rxDataLen = 0x1;
rdParams1.rxDataBuf = &ucFlashStatusReg;
rdParams1.cmdAddr = OSPI_CMD_INVALID_ADDR;
rdParams1.numAddrBytes = 0x1;
OSPI_lld_readCmd(gOspiHandle, &rdParams1);

ClockP_usleep(2000);

/* Set write enable to flash */
OSPI_WriteCmdParams_init(&wrParams1);
wrParams1.cmd = 0x06;
wrParams1.txDataLen = 0;
wrParams1.numAddrBytes = 0;
wrParams1.cmdAddr = OSPI_CMD_INVALID_ADDR;
wrParams1.txDataBuf = 0;
OSPI_lld_writeCmd(gOspiHandle, &wrParams1);

ClockP_usleep(2000);

/* Enter 4 byte address mode */
OSPI_WriteCmdParams_init(&wrParams1);
wrParams1.cmd = 0xB7;
wrParams1.txDataLen = 0;
wrParams1.numAddrBytes = 0;
wrParams1.cmdAddr = OSPI_CMD_INVALID_ADDR;
wrParams1.txDataBuf = 0;
OSPI_lld_writeCmd(gOspiHandle, &wrParams1);

ClockP_usleep(2000);

/* Set Volatile Configuration Register to work in octal DDR mode */
OSPI_WriteCmdParams_init(&wrParams1);
wrParams1.cmd = 0x81;
wrParams1.txDataLen = 1;
wrParams1.cmdAddr = 0x00;
ucFlashWriteReg = 0xE7;
wrParams1.txDataBuf = &ucFlashWriteReg;
wrParams1.numAddrBytes = 0x4;
OSPI_lld_writeCmd(gOspiHandle, &wrParams1);

ClockP_usleep(2000);

/* Clock devider (only even values, clock input is 83MHz */
OSPI_lld_configBaudrate(gOspiHandle, 0x08U);

/* Set number of lines to OSPI peripheral (also DTR mode enable from here) */
OSPI_lld_setProtocol(gOspiHandle,0x1080808U);

/* Set number of dummy cycles for read command */
OSPI_lld_setReadDummyCycles(gOspiHandle, 0x10U);

/* Set OSPI to work in 4Byte mode */
OSPI_lld_setNumAddrBytes(gOspiHandle, 0x04U);

/* Set Write/Read commands */
OSPI_lld_setXferOpCodes(gOspiHandle, 0x0C, 0x12);

CSL_REG32_FINS(0x53808004ul ,OSPI_FLASH_CFG_DEV_INSTR_RD_CONFIG_REG_DDR_EN_FLD, 1);

OSPI_phyTuneDDR(gOspiHandle, 0);

/* Fill buffers with known data,
* find block number from offset,
* erase block, write the data, read back from a specific offset
* and finally compare the results.
*/

if( SystemP_SUCCESS == status)
{
ospi_flash_diag_test_fill_buffers();

uint32_t offset = APP_OSPI_FLASH_OFFSET;

DebugP_log("[OSPI Flash Diagnostic Test] Executing Flash Erase on first block...\r\n");
status = OSPI_lld_norFlashErase(gOspiHandle, offset);
if(SystemP_SUCCESS == status)
{
DebugP_log("[OSPI Flash Diagnostic Test] Done !!!\r\n");
}
else
{
DebugP_log("[OSPI Flash Diagnostic Test] Erase Failed !!!\r\n");
}
DebugP_log("[OSPI Flash Diagnostic Test] Performing Write-Read Test...\r\n");

status = OSPI_lld_norFlashWrite(gOspiHandle, offset, gOspiTxBuf, APP_OSPI_DATA_SIZE);

if(SystemP_SUCCESS != status)
{
DebugP_log("[OSPI Flash Diagnostic Test] Wtite Failed !!!\r\n");
}
else
{
/* Nothing */
}

OSPI_lld_norFlashRead(gOspiHandle, offset, gOspiRxBuf, APP_OSPI_DATA_SIZE);

status |= ospi_flash_diag_test_compare_buffers();

if(SystemP_SUCCESS == status)
{
DebugP_log("[OSPI Flash Diagnostic Test] Write-Read Test Passed!\r\n");
}
}

if(SystemP_SUCCESS == status)
{
DebugP_log("All tests have passed!!\r\n");
}
else
{
DebugP_log("Some tests have failed!!\r\n");
}

Board_driversClose();
Drivers_close();
}