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TMS570LC4357-SEP: Operating nPORRST Pin

Dhir Gandhi
Prodigy 190 points
Part Number: TMS570LC4357-SEP
Other Parts Discussed in Thread: LAUNCHXL2-570LC43, TL7700-SEP, SN54SC4T08-SEP, TPS7H4010-SEP

Tool/software:

Hello,

I need some clarification regarding the operation of the nPORRST pin on the MCU.

In the LAUNCHXL2-570LC43 LaunchPad schematic, only the 1.2V core voltage is monitored using a voltage supervisor. There's no supervisor for the 3.3V IO supply. This raises a concern because if the 3.3V rail drops below its minimum operating voltage, it could cause unpredictable behavior on the IOs.

In contrast, the TMS570LC43x HDK EVK schematic includes voltage supervisors for both 1.2V and 3.3V.

Questions:

  1. Which approach is recommended — monitoring only 1.2V or both 1.2V and 3.3V?

  2. In my design the power sequencing is:
    1.2V (Vcore) → 3.3V (Vccio).

  3. Currently, I've pulled up the nPORRST pin to 3.3V using a 10k resistor. However, based on TI forum posts, it seems this approach is not recommended.

Proposed Solutions:

I'm considering using two TL7700-SEP voltage supervisors (one for 1.2V and one for 3.3V, their Tpo set to 1.1ms) and feeding their outputs into an AND gate (SN54SC4T08-SEP). The AND gate output would drive the MCU's nPORRST pin.

  • Is this a valid and reliable approach?

Alternatively, I'm using the TPS7H4010-SEP buck converter to generate 1.2V and 3.3V. The PGOOD output of 1.2V buck drives the EN pin of the 3.3V converter. I could also connect both PGOOD signals to the inputs of the AND gate and drive nPORRST from its output.

However, in this configuration, I'm concerned about meeting the minimum 1 ms nPORRST hold time requirement, as PGOOD signals might deassert too quickly.

Request:

Please advise:

  • Which approach is more suitable?

  • Is there a simpler or more reliable alternative to manage the nPORRST signal correctly?

  • 0
    TI__Guru 70241 points

    Hi Dhir,

    Dhir Gandhi said:
    Which approach is recommended — monitoring only 1.2V or both 1.2V and 3.3V?

    Yes, it would be better to monitor both 1.2v and 3.3v. Launchpad mainly designed for low cost and low size perspective that is the reason some of the modules are missed in Launchpad from HDK.

    Dhir Gandhi said:
    In my design the power sequencing is:
    1.2V (Vcore) → 3.3V (Vccio).

    Your power sequencing is fine.

    The only important thing is that, as long as nPORRST is held low until both power supplies stable.

    Dhir Gandhi said:
    Currently, I've pulled up the nPORRST pin to 3.3V using a 10k resistor. However, based on TI forum posts, it seems this approach is not recommended.

    You are right, just using 10k pull-up resistor to 3.3v on nPORRST is not recommended by TI.

    Give some time to verify your proposed solutions.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to Dhir Gandhi
    Prodigy 190 points

    Hello Jagadish,
    I am still awaiting your response.

    Also, could you please let me know the current consumption of OCSIN pin if I am using it with a 3.3V LVCMOS TCXO?

  • 0 in reply to Dhir Gandhi
    TI__Guru 70241 points

    Hi Gandhi,

    Dhir Gandhi said:
    Also, could you please let me know the current consumption of OCSIN pin if I am using it with a 3.3V LVCMOS TCXO?

    The current consumption on this pin depends on the whether you are using crystal oscillator or external clock source.

    If you need this data for to estimate power budgeting, then you can assume that:

    Fir external clock input you can assume ~1uA, whereas if you are using crystal oscillator then you can assume <=1mA.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 190 points
    jagadish gundavarapu said:

    Give some time to verify your proposed solutions.

    I am still awaiting your response on this.

  • 0 in reply to Dhir Gandhi
    TI__Guru 70241 points

    Hi Dhir Gandhi,

    Dhir Gandhi said:
    I am still awaiting your response on this.

    Apologies for the delay, i am not completely expert with hardware design, so i am looking for some other hardware expert colleagues help to review these solutions.

    Give me some more time to do this, maybe couple of days.

    --
    Thanks & regards,
    Jagadish.

  • +1 in reply to jagadish gundavarapu
    TI__Guru 70241 points

    Hi Dhir Gandhi,

    1. Approach 1: Two TL7700-SEP Supervisors + SN54SC4T08-SEP AND Gate

    • This approach seems Highly Valid and Reliable. This is generally the recommended approach for robust power-on reset generation.
    • Meets th(PORRST): The Tpo setting of 1.1ms on each TL7700-SEP is key. The AND gate output will remain low (asserting nPORRST) until both voltage rails are stable and their respective 1.1ms delays have passed. This guarantees that nPORRST is held low for at least 1.1ms after both supplies are stable, comfortably meeting the 1ms minimum requirement.
    • Clean Signal: Voltage supervisors are designed to provide clean, debounced reset signals, which helps with the tf(nPORRST) glitch filter requirement.
    • Radiation-Tolerant: All components are SEP-grade, suitable for your application.

    2. Approach 2: TPS7H4010-SEP PGOODs + SN54SC4T08-SEP AND Gate

    • Less Reliable, with significant concerns. Your concern about th(PORRST) is absolutely correct.
    • th(PORRST) Challenge: PGOOD signals assert as soon as the voltage is in regulation. They do not inherently provide a delay after regulation. While the buck converters have startup times, the PGOOD signal will go high very quickly once the voltage is stable. There's no built-in mechanism to hold nPORRST low for the required 1ms after stability.
    • Unpredictable Delay: The actual delay from power-on to PGOOD assertion depends on many factors (load, input voltage ramp, component tolerances, temperature). Relying on this inherent startup time to meet a minimum hold time is risky and generally not robust.

    Approach 1 (Two TL7700-SEP Supervisors + AND Gate) is significantly more suitable and reliable. It directly addresses the critical 1ms th(PORRST) hold time requirement through the configurable Tpo delay of the supervisors. This provides a guaranteed, predictable delay after the supplies are stable, ensuring the MCU is properly reset. Thoroughly test the power-on reset behavior across temperature and supply voltage variations to confirm it meets all MCU requirements.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 190 points

    Thanks Jagadish!