Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hello,
I'm working on getting EtherCAT operational on a custom board that utilizes the DP83867 PHY. I'm using the beckhoff_slave example. I am using the Ind comms SDK version 11 with AM2432 ALV
I've successfully used the DP83867 driver with an AM64x board previously, so I have some familiarity with it.
Here's what I've done and observed on the new board:
- Custom Reset Sequence: I've implemented a custom reset sequence tailored to my board's pin configuration.
- PHY Mode: I've configured the PHY to MII mode by disabling RGMII. This was done by clearing bit 7 of the
RGMII_CTRLregister (0x0032). - Sysconfig Settings: In Sysconfig, I've set up the correct pinning and strapped PHY addresses. I've also configured
link_polaritytoACTIVE_HIGH(in tiescsoc.c) for MLink fast detection, which I verified by checking theMDIO_LINK_REGSstatus. - PHYSTS Register: After auto negotiation completes, reading the
PHYSTSregister returns0x7F02. - ESC DL Status: With the main device connected to port 0, the ESC DL status register shows
0x5611. - Counters at 0xE00: When scanning for the sub-device, I can see that the counters at address
0xE00are incrementing with the correct number of messages. - TX_CLK Signal: I've verified that the
TX_CLKsignal is being generated.
The Problem:
Despite the above, the Work Counter (WKC) is not incrementing, which is causing the scanning process to fail.
Has anyone encountered a similar issue or have suggestions on what I should investigate next? Any insights would be greatly appreciated!
Thanks,
Saptarshi