Other Parts Discussed in Thread: HALCOGEN
I'm developing on TMS5570LS20216, and using HALCoGen 2.09.000 .
Take two pins as an example,MIBSPI5SOMI[1]/DMMDATA[13] pin and DMMDATA[0] pin. DMMDATA[13] is shared in DMM module and SPI5 module,
DMMDATA[0] is only used in dmm module.
And i configure DMMDATA[13] and DMMDATA[0] works in GIO mode, output, Open Drain disabled,pull functionality disabled.
DMMDATA[0] is configured in DMM registers, DMMDATA[13] is configured same in DMM and SPI5 registers.
Then i use DMM module PC4(Data Output Set Register) register and PC5(Data Output Clear Register) register to
control DMMDATA[0]/DMMDATA[13] pin output state. As expected, DMMDATA[0] pin state can works well. But DMMDATA[13] pin state can't works well, its output
state can't be controlled by DMM PC4 and PC5. so, what's the problem and how to solve ?
Here i attached the related code for your analysis:
void main(void)
{
dmmInit();
spiInit();
dmm_Clear_570ReadyPin_Low();
dmm_Set_570ReadyPin_High();
dmm_570AsSPISlave_Clear_EnablePin_Low();
dmm_570AsSPISlave_Set_EnablePin_High();
while(1)
{}
}
void dmm_Clear_570ReadyPin_Low(void)
{
dmmREG->PC5 = 0x00008000;
}
void dmm_Set_570ReadyPin_High(void)
{
dmmREG->PC4 = 0x00008000;
}
void dmm_570AsSPISlave_Set_EnablePin_High(void)
{
dmmREG->PC4 = 0x00000004;
}
void dmm_570AsSPISlave_Clear_EnablePin_Low(void)
{
dmmREG->PC5 = 0x00000004;
}
void dmmInit(void)
{
/** @b initalise @b DMM @b Port */
dmmREG->PC3 = 0 /* DMM SYNC */
| (0 << 1) /* DMM CLK */
| (1 << 2) /* DATA[0] */
| (0 << 3) /* DATA[1] */
| (0 << 4) /* DATA[2] */
| (0 << 5) /* DATA[3] */
| (0 << 6) /* DATA[4] */
| (0 << 7) /* DATA[5] */
| (0 << 8) /* DATA[6] */
| (0 << 9) /* DATA[7] */
| (0 << 10) /* DATA[8] */
| (0 << 11) /* DATA[9] */
| (0 << 12) /* DATA[10] */
| (0 << 13) /* DATA[11] */
| (0 << 14) /* DATA[12] */
| (1 << 15) /* DATA[13] */
| (0 << 16) /* DATA[14] */
| (0 << 17) /* DATA[15] */
| (0 << 18); /* DMM ENA */
/** - DMM Port direction */
dmmREG->PC1 = 0 /* DMM SYNC */
| (0 << 1) /* DMM CLK */
| (1 << 2) /* DATA[0] */
| (0 << 3) /* DATA[1] */
| (0 << 4) /* DATA[2] */
| (0 << 5) /* DATA[3] */
| (0 << 6) /* DATA[4] */
| (0 << 7) /* DATA[5] */
| (0 << 8) /* DATA[6] */
| (0 << 9) /* DATA[7] */
| (0 << 10) /* DATA[8] */
| (0 << 11) /* DATA[9] */
| (0 << 12) /* DATA[10] */
| (0 << 13) /* DATA[11] */
| (0 << 14) /* DATA[12] */
| (1 << 15) /* DATA[13] */
| (0 << 16) /* DATA[14] */
| (0 << 17) /* DATA[15] */
| (0 << 18); /* DMM ENA */
/** - DMM Port open drain enable */
dmmREG->PC6 = 0 /* DMM SYNC */
| (0 << 1) /* DMM CLK */
| (0 << 2) /* DATA[0] */
| (0 << 3) /* DATA[1] */
| (0 << 4) /* DATA[2] */
| (0 << 5) /* DATA[3] */
| (0 << 6) /* DATA[4] */
| (0 << 7) /* DATA[5] */
| (0 << 8) /* DATA[6] */
| (0 << 9) /* DATA[7] */
| (0 << 10) /* DATA[8] */
| (0 << 11) /* DATA[9] */
| (0 << 12) /* DATA[10] */
| (0 << 13) /* DATA[11] */
| (0 << 14) /* DATA[12] */
| (0 << 15) /* DATA[13] */
| (0 << 16) /* DATA[14] */
| (0 << 17) /* DATA[15] */
| (0 << 18); /* DMM ENA */
/** - DMM Port pullup / pulldown selection */
dmmREG->PC8 = 0 /* DMM SYNC */
| (0 << 1) /* DMM CLK */
| (0 << 2) /* DATA[0] */
| (0 << 3) /* DATA[1] */
| (0 << 4) /* DATA[2] */
| (0 << 5) /* DATA[3] */
| (0 << 6) /* DATA[4] */
| (0 << 7) /* DATA[5] */
| (0 << 8) /* DATA[6] */
| (0 << 9) /* DATA[7] */
| (0 << 10) /* DATA[8] */
| (0 << 11) /* DATA[9] */
| (0 << 12) /* DATA[10] */
| (0 << 13) /* DATA[11] */
| (0 << 14) /* DATA[12] */
| (0 << 15) /* DATA[13] */
| (0 << 16) /* DATA[14] */
| (0 << 17) /* DATA[15] */
| (0 << 18); /* DMM ENA */
/** - DMM Port pullup / pulldown enable*/
dmmREG->PC7 = 1 /* DMM SYNC */
| (1 << 1) /* DMM CLK */
| (1 << 2) /* DATA[0] */
| (1 << 3) /* DATA[1] */
| (1 << 4) /* DATA[2] */
| (1 << 5) /* DATA[3] */
| (1 << 6) /* DATA[4] */
| (1 << 7) /* DATA[5] */
| (1 << 8) /* DATA[6] */
| (1 << 9) /* DATA[7] */
| (1 << 10) /* DATA[8] */
| (1 << 11) /* DATA[9] */
| (1 << 12) /* DATA[10] */
| (1 << 13) /* DATA[11] */
| (1 << 14) /* DATA[12] */
| (1 << 15) /* DATA[13] */
| (1 << 16) /* DATA[14] */
| (1 << 17) /* DATA[15] */
| (1 << 18); /* DMM ENA */
/* DMM set all pins to functional */
dmmREG->PC0 = 0 /* DMM SYNC */
| (0 << 1) /* DMM CLK */
| (0 << 2) /* DATA[0] */
| (0 << 3) /* DATA[1] */
| (0 << 4) /* DATA[2] */
| (0 << 5) /* DATA[3] */
| (0 << 6) /* DATA[4] */
| (0 << 7) /* DATA[5] */
| (0 << 8) /* DATA[6] */
| (0 << 9) /* DATA[7] */
| (0 << 10) /* DATA[8] */
| (0 << 11) /* DATA[9] */
| (0 << 12) /* DATA[10] */
| (0 << 13) /* DATA[11] */
| (0 << 14) /* DATA[12] */
| (0 << 15) /* DATA[13] */
| (0 << 16) /* DATA[14] */
| (0 << 17) /* DATA[15] */
| (0 << 18); /* DMM ENA */
}
void spiInit(void)
{
/*skip other unrelated code here*/
......
spiREG5->PCDOUT = 0 /* SCS[0] */
| (0 << 1) /* SCS[1] */
| (0 << 2) /* SCS[2] */
| (0 << 3) /* SCS[3] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11) /* SOMI */
| (1 << 25); /* SOMI[1]/DMMData[13] */
/** - SPI5 Port direction */
spiREG5->PCDIR = 0 /* SCS[0] */
| (0 << 1) /* SCS[1] */
| (0 << 2) /* SCS[2] */
| (0 << 3) /* SCS[3] */
| (1 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11) /* SOMI */
| (1 << 25); /* SOMI[1]/DMMData[13] */
/** - SPI5 Port open drain enable */
spiREG5->PCPDR = 0 /* SCS[0] */
| (0 << 1) /* SCS[1] */
| (0 << 2) /* SCS[2] */
| (0 << 3) /* SCS[3] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11) /* SOMI */
| (0 << 25); /* SOMI[1]/DMMData[13] */
/** - SPI5 Port pullup / pulldown selection */
spiREG5->PCPSL = 0 /* SCS[0] */
| (1 << 1) /* SCS[1] */
| (1 << 2) /* SCS[2] */
| (1 << 3) /* SCS[3] */
| (0 << 8) /* ENA */
| (0 << 9) /* CLK */
| (0 << 10) /* SIMO */
| (0 << 11) /* SOMI */
| (0 << 25); /* SOMI[1]/DMMData[13] */
/** - SPI5 Port pullup / pulldown enable*/
spiREG5->PCDIS = 1 /* SCS[0] */
| (0 << 1) /* SCS[1] */
| (0 << 2) /* SCS[2] */
| (0 << 3) /* SCS[3] */
| (1 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11) /* SOMI */
| (1 << 25); /* SOMI[1]/DMMData[13] */
/* SPI5 set all pins to functional */
spiREG5->PCFUN = 1 /* SCS[0] */
| (0 << 1) /* SCS[1] */
| (0 << 2) /* SCS[2] */
| (0 << 3) /* SCS[3] */
| (0 << 8) /* ENA */
| (1 << 9) /* CLK */
| (1 << 10) /* SIMO */
| (1 << 11) /* SOMI */
| (0 << 25); /* SOMI[1]/DMMData[13] */
/** - Finaly start SPI5 */
spiREG5->ENA = 1U;
}
