AM263P4: Clarification request for erratum i2485 on AM263P4

Tool/software:

Dear TI team,

while reviewing erratum i2485 (“[TMU] TCM Memory Corruption on R5SS0_CORE1 and R5SS1_CORE1...”) in the latest AM263P4 documentation, I found the description unclear in several critical aspects. I'd like to request clarification regarding the following points:

1. Applicability to lockstep mode:

   The erratum refers to “R5SS0_CORE1 and R5SS1_CORE1” accessing TMU registers, with corruption occurring in ATCM1 Bank0 memory when using the TMU via the TCM interface. However, these _CORE1 instances only exist when the corresponding R5SS is configured in split mode. The text does not specify whether this issue also applies when the subsystem is in lockstep mode – i.e., when _CORE1 is shadowing _CORE0.

   Could you please confirm:

   • Is this issue only present in split mode when _CORE1 is independently executing code?

   • Or can the corruption also occur in lockstep mode due to CORE1 mirroring writes initiated by CORE0?

   This is important because in lockstep mode, the memory interface activity of CORE1 may still affect the bus arbitration or write enables, depending on the TMU integration.

2. Inconsistent terminology – “CPU0” vs CORE naming:

   Workaround WA2 says “Use CPU0 TMU alone…”, while the erratum body refers explicitly to R5SSx_CORE1. The term “CPU0” is ambiguous in the context of AM263P4, which does not explicitly define such naming in the TRM. Is “CPU0” referring to R5SS0_CORE0 (and possibly also R5SS1_CORE0) in split mode?

   For clarification:

   • Does WA2 mean that only the _CORE0 of each R5SS cluster should be used for TMU accesses?

   • Or does it refer only to R5SS0_CORE0, implying that TMU usage should be limited to a specific cluster (e.g., R5FSS0) entirely?

We are evaluating whether to use TMU from both cores in split mode or restrict usage to one core per cluster – and this erratum has significant implications.

Thank you in advance for your support and clarification.

Best regards,
Jiri