This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2432: Ethercat msater demo

Part Number: AM2432
Other Parts Discussed in Thread: LP-AM243, DP83869, UNIFLASH

Tool/software:

I download motor_control_sdk_am243x_09_02_00_11 and  use ethercat_slave_simple_demo_am243x-lp_r5fss0-0_freertos_ti-arm-clang project.

I try to write a ethercat master demo on igh ethercat。but when runing ,I have some errors。

AM243X log:

Friendly Version: <KB OSAL v00.01.02.02>
Source Id: <5e1ebb0ccfdbbbe7667ebf41c1452faab7e5228b>
*********************************************************************
State change: 0x0 -> 0x1
SSC_checkTimer:MaxD:9267640 (9)
SSC_checkTimer:MaxET:4
SSC_checkTimer:MaxD:11999745 (11)
State change: 0x1 -> 0x2
State change: 0x2 -> 0x1
State change: 0x1 -> 0x2
State change: 0x2 -> 0x1
State change: 0x1 -> 0x2

master log:

Requesting master...
Creating slave configurations...
Activating master...
Starting my_task...
[ 6729.946106] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
[ 6729.951106] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).
[ 6729.953105] EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".

demo code.

/*****************************************************************************
 *
 *  Copyright (C) 2009-2010  Moehwald GmbH B. Benner
 *                     2011  IgH Andreas Stewering-Bone
 *                     2012  Florian Pose <fp@igh.de>
 *
 *  This file is part of the IgH EtherCAT master
 *
 *  The IgH EtherCAT Master is free software; you can redistribute it and/or
 *  modify it under the terms of the GNU General Public License version 2, as
 *  published by the Free Software Foundation.
 *
 *  The IgH EtherCAT master is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
 *  Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License along
 *  with the IgH EtherCAT master. If not, see <http://www.gnu.org/licenses/>.
 *
 ****************************************************************************/

#include <errno.h>
#include <signal.h>
#include <stdio.h>
#include <string.h>
#include <sys/resource.h>
#include <sys/time.h>
#include <sys/types.h>
#include <unistd.h>
#include <sys/mman.h>
#ifdef XENOMAI_API_V3
#include <alchemy/task.h>
#include <alchemy/sem.h>
enum {T_FPU = 0};
#else
#include <rtdm/rtdm.h>
#include <native/task.h>
#include <native/sem.h>
#include <native/mutex.h>
#include <native/timer.h>
#include <rtdk.h>
#endif
#include <pthread.h>
#include <time.h>
#include "ecrt.h"

RT_TASK my_task;

static volatile sig_atomic_t run = 1;

/****************************************************************************/

// EtherCAT
static ec_master_t *master = NULL;
static ec_master_state_t master_state = {};

static ec_domain_t *domain1 = NULL;
static ec_domain_state_t domain1_state = {};

static uint8_t *domain1_pd = NULL;

static ec_slave_config_t *sc_dig_out_01 = NULL;

/****************************************************************************/

// process data

#define TISlaveDemo_Pos 0, 0

//TI EtherCAT Toolkit for AM243X.R5F

#define Beckhoff_TI_AM243X 0xe000059D, 0x54490025


// offsets for PDO entries
static unsigned int off_dig_out0 = 0;

// process data

const static ec_pdo_entry_reg_t domain1_regs[] = {
   {TISlaveDemo_Pos, Beckhoff_TI_AM243X, 0x2000, 0x02, &off_dig_out0, NULL},
   {}
};

/****************************************************************************/

/* Slave 1, "TI"
 * Vendor ID:       0xe000059D
 * Product code:    0x54490025
 * Revision number: 0x00010000
 */


const ec_pdo_entry_info_t master_pdo_entries[] = {

    {0x2000, 0x02, 8},
    {0x2000, 0x03, 8}, 
    {0x2000, 0x04, 16}, 
    

    {0x2000, 0x01, 32},
    

    {0x2002, 0x02, 8}, 
    {0x2002, 0x04, 16}, 
    {0x2002, 0x03, 8},
    

    {0x2002, 0x01, 32}, 
};


const ec_pdo_info_t master_pdos[] = {

    {0x1600, 3, master_pdo_entries},
    

    {0x1601, 1, master_pdo_entries + 3}, 
    

    {0x1A00, 3, master_pdo_entries + 4},  
    

    {0x1A01, 1, master_pdo_entries + 7}, 
};


ec_sync_info_t slave_1_syncs[] = {
    {0, EC_DIR_OUTPUT, 2, master_pdos + 0, EC_WD_ENABLE},
    
    {1, EC_DIR_INPUT, 2, master_pdos + 2, EC_WD_ENABLE},
    
    {0xff}
};

/*****************************************************************************
 * Realtime task
 ****************************************************************************/

void rt_check_domain_state(void)
{
    ec_domain_state_t ds = {};

	ecrt_domain_state(domain1, &ds);

    if (ds.working_counter != domain1_state.working_counter) {
        rt_printf("Domain1: WC %u.\n", ds.working_counter);
    }

    if (ds.wc_state != domain1_state.wc_state) {
        rt_printf("Domain1: State %u.\n", ds.wc_state);
    }

    domain1_state = ds;
}

/****************************************************************************/

void rt_check_master_state(void)
{
    ec_master_state_t ms;

	ecrt_master_state(master, &ms);

    if (ms.slaves_responding != master_state.slaves_responding) {
        rt_printf("%u slave(s).\n", ms.slaves_responding);
    }

    if (ms.al_states != master_state.al_states) {
        rt_printf("AL states: 0x%02X.\n", ms.al_states);
    }

    if (ms.link_up != master_state.link_up) {
        rt_printf("Link is %s.\n", ms.link_up ? "up" : "down");
    }

    master_state = ms;
}

/****************************************************************************/

void my_task_proc(void *arg)
{
	int cycle_counter = 0;
    int time_counter = 0;
    unsigned int blink = 0;
    struct timespec start, end;
    double tx_time = 0;
    double rx_time = 0;
    double tx_min_time = 0;
    double tx_max_time = 0;
    double rx_min_time = 0;
    double rx_max_time = 0;
    double tx_avg_time = 0;
    double rx_avg_time = 0;
    double tx_total_time = 0;
    double rx_total_time = 0;
    int rx_init = 0;
    int tx_init = 0;
    int warmup = 0;
	rt_task_set_periodic(NULL, TM_NOW, 1000000); // ns

	while (run) {
		rt_task_wait_period(NULL);

		cycle_counter++;
        clock_gettime(CLOCK_MONOTONIC, &start);
		// receive EtherCAT frames
		ecrt_master_receive(master);
        clock_gettime(CLOCK_MONOTONIC, &end);
		ecrt_domain_process(domain1);
        if(warmup > 2) /* wait 2s */
        {
            time_counter++;
            rx_time = ((end.tv_sec - start.tv_sec) * 1e9 + (end.tv_nsec - start.tv_nsec))/1000;
            if(!rx_init)
            {
                rx_init = 1;
                rx_min_time = rx_time;
            }
            if(rx_time < rx_min_time)
            {
                rx_min_time = rx_time;
            }
            if(rx_time > rx_max_time)
            {
                rx_max_time = rx_time;
                printf("[rx max]: max:%.2f us\n",rx_max_time);
            }
            rx_total_time += rx_time;
            rx_avg_time = rx_total_time/time_counter;
        }
		rt_check_domain_state();

		if (!(cycle_counter % 1000)) {
            warmup++;
			rt_check_master_state();
            if(warmup > 2) /* wait 2s */
            {
                printf("[rx]: curr:%.2f us | min:%.2f us | avg:%.2f us | max:%.2f us\n", rx_time, rx_min_time, rx_avg_time, rx_max_time);
                printf("[tx]: curr:%.2f us | min:%.2f us | avg:%.2f us | max:%.2f us\n", tx_time, tx_min_time, tx_avg_time, tx_max_time);
            }
        }

		if (!(cycle_counter % 200)) {
			blink = !blink;
		}

		EC_WRITE_U8(domain1_pd + off_dig_out0, blink ? 0x0 : 0x0F);

		// send process data
        
		ecrt_domain_queue(domain1);
        clock_gettime(CLOCK_MONOTONIC, &start);
		ecrt_master_send(master);
        clock_gettime(CLOCK_MONOTONIC, &end);
        if(warmup > 2) /* wait 2s */
        {
            tx_time = ((end.tv_sec - start.tv_sec) * 1e9 + (end.tv_nsec - start.tv_nsec))/1000;
            if(!tx_init)
            {
                tx_init = 1;
                tx_min_time = tx_time;
            }
            tx_avg_time += tx_time;
            if(tx_time < tx_min_time)
            {
                tx_min_time = tx_time;
            }
            if(tx_time > tx_max_time)
            {
                tx_max_time = tx_time;
                printf("[tx max]: max:%.2f us\n",tx_max_time);
            }
            tx_total_time += tx_time;
            tx_avg_time = tx_total_time/time_counter;
        }
        
	}
}

/****************************************************************************
 * Signal handler
 ***************************************************************************/

void signal_handler(int sig)
{
    run = 0;
}

/****************************************************************************
 * Main function
 ***************************************************************************/

int main(int argc, char *argv[])
{
    ec_slave_config_t *sc;
    int ret;

#ifndef XENOMAI_API_V3
    /* Perform auto-init of rt_print buffers if the task doesn't do so */
    rt_print_auto_init(1);
#endif

    signal(SIGTERM, signal_handler);
    signal(SIGINT, signal_handler);

    mlockall(MCL_CURRENT | MCL_FUTURE);

    printf("Requesting master...\n");
    master = ecrt_request_master(0);
    if (!master) {
        return -1;
    }

    domain1 = ecrt_master_create_domain(master);
    if (!domain1) {
        return -1;
    }

    printf("Creating slave configurations...\n");

    sc_dig_out_01 =
        ecrt_master_slave_config(master, TISlaveDemo_Pos, Beckhoff_TI_AM243X);
    if (!sc_dig_out_01) {
        fprintf(stderr, "Failed to get slave configuration.\n");
        return -1;
    }

    if (ecrt_slave_config_pdos(sc_dig_out_01, EC_END, slave_1_syncs)) {
        fprintf(stderr, "Failed to configure PDOs.\n");
        return -1;
    }

    if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) {
        fprintf(stderr, "PDO entry registration failed!\n");
        return -1;
    }

    printf("Activating master...\n");
    if (ecrt_master_activate(master)) {
        return -1;
    }

    if (!(domain1_pd = ecrt_domain_data(domain1))) {
        fprintf(stderr, "Failed to get domain data pointer.\n");
        return -1;
    }

    ret = rt_task_create(&my_task, "my_task", 0, 80, T_FPU);
    if (ret < 0) {
        fprintf(stderr, "Failed to create task: %s\n", strerror(-ret));
        return -1;
    }

    printf("Starting my_task...\n");
    ret = rt_task_start(&my_task, &my_task_proc, NULL);
    if (ret < 0) {
        fprintf(stderr, "Failed to start task: %s\n", strerror(-ret));
        return -1;
    }

	while (run) {
		sched_yield();
	}

    printf("Deleting realtime task...\n");
    rt_task_delete(&my_task);

    printf("End of Program\n");
    ecrt_release_master(master);

    return 0;
}

/****************************************************************************/

I don't know what's reason, Can you provide a sample master demo based on igh ethercat?

  • Hi Wang Tao, 

    Can you explain what TI processor are you setting up IgH EtherCAT master on? Also, I understand that AM243x is running the EtherCAT slave example, I'm assuming this is the TI LP-AM243? 

    Also, are you using IgH generic stack or IgH native stack?

    Can you try the IgH main.c that I linked here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1517508/am6442-ethercat-master-cant-be-able-to-connect-slave-device/5846702#5846702 

    Below are notes I had on why I had to use the version of main.c I linked in the other thread. The error messages appears to closely align with the messages you are seeing.

    • EtherCAT WARNING 0: No application time received up to now, but master already active.
    • EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused to state change (PREOP + ERROR).
    • EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".
    • This is followed by multiple EtherCAT WARNINGS about datagram UNMATCHED and datagram skipped 1 time --> see console log in host PC
    • Fix: use ethercat/examples/dc_user/main.c since this example uses ecrt_master_application_time() which gets rid of the above issues

    Please note my responses to this thread will be delayed as I'm currently out of office and will be back next week.

    -Daolin

  • it is TI LP-AM243.

    I use maic.c you provided,Startup error, is there something wrong with the code?

    root@lubancat:/home/cat# ./ec_dc_user_example
    [ 66.483956] EtherCAT ERROR 0 0:0: PDO entry 0x2000:02 is not mapped.
    Failed to register PDO entry: No such file or directory

  • The main.c you provided is not based on LP-243. Can you provide a master demo of igh and verify that it can communicate successfully with LP-243?

  • I modified the slave code and added the printing of alErrorCode.
    OSAL_printf("State change: 0x%x -> 0x%x errorcode:0x%x\r\n", lastState, curState, alErrorCode);

    error = EC_API_SLV_getState(pApplicationInstace->ptEcSlvApi, &curState, &alErrorCode);
            if (EC_API_eERR_NONE != error)
            {
                OSAL_printf("%s:%d:E=0x%x\r\n", __func__, __LINE__, error);
            }
    
            if (curState != lastState)
            {
                OSAL_printf("State change: 0x%x -> 0x%x errorcode:0x%x\r\n", lastState, curState, alErrorCode);
                pApplicationInstace->prev = ESL_OS_clockGet();
            }
            lastState = curState;

    AM243 log:

    State change: 0x12 -> 0x2 errorcode:0x0
    State change: 0x2 -> 0x1 errorcode:0x0
    State change: 0x1 -> 0x2 errorcode:0x0
    State change: 0x2 -> 0x12 errorcode:0x1e
    State change: 0x12 -> 0x2 errorcode:0x0
    State change: 0x2 -> 0x1 errorcode:0x0
    State change: 0x1 -> 0x2 errorcode:0x0
    State change: 0x2 -> 0x12 errorcode:0x1e
    State change: 0x12 -> 0x2 errorcode:0x0

    ecSlvApiDef_error.h

    EC_API_eERR_READ_ONLY            = EC_ERROR_CLASS(0x001D),
    EC_API_eERR_OBJECT_DICT_CREATE   = EC_ERROR_CLASS(0x001E),
    EC_API_eERR_VENDOR_ID_NOT_SET    = EC_ERROR_CLASS(0x001F),
    What is the reason for this?
  • Hi Wang Tao, 

    The main.c you provided is not based on LP-243. Can you provide a master demo of igh and verify that it can communicate successfully with LP-243?

    I currently do not have a version of the main.c that is based on LP-243 but from my understanding changing it to use LP-243 should be straightforward. I believe it should just be a matter of changing the following line to match what you would need to test with LP-243 as a subdevice/slave.

    #define AM64X    0x0000059D, 0x54490022     //--> was 0xE000059D in mainv2.c but both work
    ^change to AM243x and the correct numbers for AM243x
    
    if (!(sc = ecrt_master_slave_config(
                    master, DigOutSlavePos, AM243x))) {
        fprintf(stderr, "Failed to get slave configuration.\n");
        return -1;
    }
    ^changed to reference AM243x 

    As a note, the main.c I shared was something I tested a while back so it might be possible it won't fully work on your system (my setup back then if I remember correctly was AM62x TI SKEVM as EtherCAT master connected to AM64x EVM as a subdevice). As a disclaimer, I cannot promise that I will be able to verify on LP-243 when I am back in office as I need some time to handle several other tasks on my workload. 

    I modified the slave code and added the printing of alErrorCode.
    OSAL_printf("State change: 0x%x -> 0x%x errorcode:0x%x\r\n", lastState, curState, alErrorCode);

    Regarding, the modification to the slave code, let me loop in an expert on the EtherCAT slave code. Please kindly ping this thread if you don't hear a response by Monday.

    -Daolin

  • Hi Wang Tao,

    State change: 0x2 -> 0x12 errorcode:0x1e
    • I'll loop in the EtherCAT stack expert to help you back track and root-cause the error you're seeing.
    • Also, is the error code aligning with the value you are observing in 0x134 ESC Register space (Physical offset: 0x30090134) ?

    On an additional note, I highly recommend you to use the latest EtherCAT PRU Firmware available in INDUSTRIAL COMMUNICATIONS SDK AM243X v11.00.00.08 as it contains some critical fixes for IgH and SOEM related functionality. As you can see from the Motor Control SDK structure, it uses ind_comms_sdk (Industrial Communications SDK) which itself is an independent SDK available at the above link. The Motor Control SDK v09.02.00.11 uses an older Industrial Communications SDK (v09.02.00.15) and hence, the latest fixes aren't available in your project.

    You can use motor_control_sdk_am243x_09_02_00_11 and just replace the EtherCAT firmware headers. Please follow the steps mentioned in EtherCAT Firmware Migration guide to use the latest firmware headers. In your case, you can pick the firmware headers from the specified location and replace it with the ones present motor_control_sdk_am243x_09_02_00_11\ind_comms_sdk\source\industrial_comms\ethercat_slave\icss_fwhal\firmware\g_v1.3. Post this, rebuild the libraries and rebuild the EtherCAT application.

    Additionally, you can refer to Release Notes 11.00.00 and Release Notes 09.02.00 for the fixes done in each release after IND COMMS SDK v09.02.00.15 and additional details for the firmware fixes available at ind_comms_sdk_am243x_11_00_00_08\docs\EtherCAT_SubDevice_Errata.pdf.

    Regards,
    Aaron

  • Hi Wang Tao,

    Also, is the error code aligning with the value you are observing in 0x134 ESC Register space (Physical offset: 0x30090134) ?

    Following up with my previous message, can you make sure the SM configuration (input and output) are correctly configured and aligning with the ESI configuration?

    With respect to Beckhoff Stack implementation, the error code 0x1E corresponds to ALSTATUSCODE_INVALIDSMINCFG. This is set in the case of mismatch in the SM input length configuration.

    Regards,
    Aaron

  • I use   INDUSTRIAL COMMUNICATIONS SDK AM243X v11.00.00.08

    ethercat_subdevice_simple_demo_am243x-lp_r5fss0-0_freertos_ti-arm-clang

    MCU log:

    Local Implementation
    Pruicss max =3 selected PRU:3
    Phy Reset: 0.28
    Phy Reset: 0.20
    pRegPerm = 0x30082000, dram1=0x30082000, offset = 0x00000000, size = 0x00001400
    PRU ESC: Rev 0690 | Bld 0536 | INTC base: 0x300a0000 , id = 0x4e82a900
    INTC.HIDISR addr: 0x300a0038
    RxPDO created 0x1600: 0x70139da0
    RxPDO created 0x1601: 0x70139ea8
    TxPDO created 0x1A00: 0x70139f40
    TxPDO created 0x1A01: 0x7013a048
    EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40

    The master cannot recognize slave at all, and the board lights of am243 are not in the right state, and the lights of the network port are not blinking. I think the sdk demo you mentioned cannot work properly on the board.

    In addition, I found that the same program was allowed multiple times, and occasionally it would succeed, but most of the time it would fail, and the MCU would report an error of 0x1e. This is my program, can you confirm whether it is a program problem?

    main.c

    /*****************************************************************************
     *
     *  Copyright (C) 2007-2022  Florian Pose, Ingenieurgemeinschaft IgH
     *
     *  This file is part of the IgH EtherCAT Master.
     *
     *  The IgH EtherCAT Master is free software; you can redistribute it and/or
     *  modify it under the terms of the GNU General Public License version 2, as
     *  published by the Free Software Foundation.
     *
     *  The IgH EtherCAT Master is distributed in the hope that it will be useful,
     *  but WITHOUT ANY WARRANTY; without even the implied warranty of
     *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General
     *  Public License for more details.
     *
     *  You should have received a copy of the GNU General Public License along
     *  with the IgH EtherCAT Master; if not, write to the Free Software
     *  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
     *
     ****************************************************************************/
    
    #include <errno.h>
    #include <signal.h>
    #include <stdio.h>
    #include <string.h>
    #include <sys/resource.h>
    #include <sys/time.h>
    #include <sys/types.h>
    #include <unistd.h>
    #include <time.h>
    #include <sys/mman.h>
    #include <malloc.h>
    #include <sched.h> /* sched_setscheduler() */
    
    /****************************************************************************/
    
    #include "ecrt.h"
    
    /****************************************************************************/
    
    // Application parameters
    #define FREQUENCY 1000
    #define CLOCK_TO_USE CLOCK_MONOTONIC
    #define MEASURE_TIMING
    
    /****************************************************************************/
    
    #define NSEC_PER_SEC (1000000000L)
    #define PERIOD_NS (NSEC_PER_SEC / FREQUENCY)
    
    #define DIFF_NS(A, B) (((B).tv_sec - (A).tv_sec) * NSEC_PER_SEC + \
            (B).tv_nsec - (A).tv_nsec)
    
    #define TIMESPEC2NS(T) ((uint64_t) (T).tv_sec * NSEC_PER_SEC + (T).tv_nsec)
    
    /****************************************************************************/
    
    // EtherCAT
    static ec_master_t *master = NULL;
    static ec_master_state_t master_state = {};
    
    static ec_domain_t *domain1 = NULL;
    static ec_domain_state_t domain1_state = {};
    static ec_slave_config_t *sc;
    static ec_slave_config_state_t sc_ana_in_state = {};
    /****************************************************************************/
    
    // process data
    static uint8_t *domain1_pd = NULL;
    
    #define BusCouplerPos    0, 0
    #define DigOutSlavePos   0, 1
    #define CounterSlavePos  0, 2
    
    #define Beckhoff_EK1100 0x00000002, 0x044c2c52
    #define Beckhoff_EL2008 0x00000002, 0x07d83052
    #define IDS_Counter     0x000012ad, 0x05de3052
    
    // offsets for PDO entries
    static int off_dig_out;
    static int off_counter_in;
    static int off_counter_out;
    
    static unsigned int counter = 0;
    static unsigned int blink = 0;
    static unsigned int sync_ref_counter = 0;
    const struct timespec cycletime = {0, PERIOD_NS};
    
    // process data
    
    #define TISlaveDemo_Pos 0, 0
    
    //TI EtherCAT Toolkit for AM243X.R5F
    
    #define Beckhoff_TI_AM243X 0xe000059D, 0x54490025
    
    
    // offsets for PDO entries
    static unsigned int off_dig_out0 = 0;
    
    // process data
    
    const static ec_pdo_entry_reg_t domain1_regs[] = {
       {TISlaveDemo_Pos, Beckhoff_TI_AM243X, 0x2000, 0x02, &off_dig_out0, NULL},
       {}
    };
    
    /****************************************************************************/
    
    /* Slave 1, "TI"
     * Vendor ID:       0xe000059D
     * Product code:    0x54490025
     * Revision number: 0x00010000
     */
    
    const ec_pdo_entry_info_t master_pdo_entries[] = {
        {0x2000, 0x02, 8}, 
        {0x2000, 0x03, 8},  
        {0x2000, 0x04, 16},  
        {0x2000, 0x01, 32},
        {0x2002, 0x02, 8},   
        {0x2002, 0x04, 16},  
        {0x2002, 0x03, 8},   
        {0x2002, 0x01, 32}, 
    };
    
    // 主站PDO组配置
    const ec_pdo_info_t master_pdos[] = {
        {0x1600, 3, master_pdo_entries},
        {0x1601, 1, master_pdo_entries + 3},
        {0x1A00, 3, master_pdo_entries + 4},
        {0x1A01, 1, master_pdo_entries + 7}, 
    };
    
    
    ec_sync_info_t slave_1_syncs[] = {
    
        {0, EC_DIR_OUTPUT, 0, NULL, EC_WD_DISABLE},                                              
        {1, EC_DIR_INPUT, 0, NULL, EC_WD_DISABLE},    
        {2, EC_DIR_OUTPUT, 2, master_pdos + 0, EC_WD_ENABLE},
        {3, EC_DIR_INPUT, 2, master_pdos + 2, EC_WD_ENABLE},
        
        {0xff}
    };
    
    /****************************************************************************/
    
    struct timespec timespec_add(struct timespec time1, struct timespec time2)
    {
        struct timespec result;
    
        if ((time1.tv_nsec + time2.tv_nsec) >= NSEC_PER_SEC) {
            result.tv_sec = time1.tv_sec + time2.tv_sec + 1;
            result.tv_nsec = time1.tv_nsec + time2.tv_nsec - NSEC_PER_SEC;
        } else {
            result.tv_sec = time1.tv_sec + time2.tv_sec;
            result.tv_nsec = time1.tv_nsec + time2.tv_nsec;
        }
    
        return result;
    }
    
    /****************************************************************************/
    
    void check_domain1_state(void)
    {
        ec_domain_state_t ds;
    
        ecrt_domain_state(domain1, &ds);
    
        if (ds.working_counter != domain1_state.working_counter)
            printf("Domain1: WC %u.\n", ds.working_counter);
        if (ds.wc_state != domain1_state.wc_state)
            printf("Domain1: State %u.\n", ds.wc_state);
    
        domain1_state = ds;
    }
    
    /****************************************************************************/
    
    void check_master_state(void)
    {
        ec_master_state_t ms;
    
        ecrt_master_state(master, &ms);
    
        if (ms.slaves_responding != master_state.slaves_responding)
            printf("%u slave(s).\n", ms.slaves_responding);
        if (ms.al_states != master_state.al_states)
            printf("AL states: 0x%02X.\n", ms.al_states);
        if (ms.link_up != master_state.link_up)
            printf("Link is %s.\n", ms.link_up ? "up" : "down");
    
        master_state = ms;
    }
    
    /****************************************************************************/
    
    void check_slave_config_states(void)
    {
        ec_slave_config_state_t s;
    
        ecrt_slave_config_state(sc, &s);
    
        if (s.al_state != sc_ana_in_state.al_state) {
            printf("AnaIn: State 0x%02X.\n", s.al_state);
        }
        if (s.online != sc_ana_in_state.online) {
            printf("AnaIn: %s.\n", s.online ? "online" : "offline");
        }
        if (s.operational != sc_ana_in_state.operational) {
            printf("AnaIn: %soperational.\n", s.operational ? "" : "Not ");
        }
    
        sc_ana_in_state = s;
    }
    
    void cyclic_task()
    {
        struct timespec wakeupTime, time;
    #ifdef MEASURE_TIMING
        struct timespec startTime, endTime, lastStartTime, startSendTime, endSendTime, sendTime, recvTime = {};
        uint32_t period_ns = 0, exec_ns = 0, latency_ns = 0, send_ns, recv_ns = 0,
                 latency_min_ns = 0, latency_max_ns = 0,
                 period_min_ns = 0, period_max_ns = 0,
                 exec_min_ns = 0, exec_max_ns = 0,
                 send_min_ns = 0, send_max_ns = 0,
                 recv_min_ns = 0, recv_max_ns = 0;
        uint64_t total_send_time = 0, send_avg_time = 0;;
        uint64_t total_recv_time = 0, recv_avg_time = 0;
        uint64_t cyclic_cnt = 0;
    #endif
    
        // get current time
        clock_gettime(CLOCK_TO_USE, &wakeupTime);
    
        while(1) {
            wakeupTime = timespec_add(wakeupTime, cycletime);
            clock_nanosleep(CLOCK_TO_USE, TIMER_ABSTIME, &wakeupTime, NULL);
            cyclic_cnt++;
            // Write application time to master
            //
            // It is a good idea to use the target time (not the measured time) as
            // application time, because it is more stable.
            //
            ecrt_master_application_time(master, TIMESPEC2NS(wakeupTime));
    
    #ifdef MEASURE_TIMING
            clock_gettime(CLOCK_TO_USE, &startTime);
            latency_ns = DIFF_NS(wakeupTime, startTime);
            period_ns = DIFF_NS(lastStartTime, startTime);
            exec_ns = DIFF_NS(lastStartTime, endTime);
            lastStartTime = startTime;
    
            if (latency_ns > latency_max_ns) {
                latency_max_ns = latency_ns;
            }
            if (latency_ns < latency_min_ns) {
                latency_min_ns = latency_ns;
            }
            if (period_ns > period_max_ns) {
                period_max_ns = period_ns;
            }
            if (period_ns < period_min_ns) {
                period_min_ns = period_ns;
            }
            if (exec_ns > exec_max_ns) {
                exec_max_ns = exec_ns;
            }
            if (exec_ns < exec_min_ns) {
                exec_min_ns = exec_ns;
            }
            
    #endif
    
            // receive process data
            ecrt_master_receive(master);
            clock_gettime(CLOCK_TO_USE, &recvTime);
            recv_ns = DIFF_NS(startTime, recvTime);
            if (recv_ns > recv_max_ns) {
                recv_max_ns = recv_ns;
            }
            if (recv_ns < recv_min_ns) {
                recv_min_ns = recv_ns;
            }
            total_recv_time += recv_ns;
            recv_avg_time = total_recv_time/cyclic_cnt;
            ecrt_domain_process(domain1);
    
            // check process data state (optional)
            check_domain1_state();
    
            if (counter) {
                counter--;
            } else { // do this at 1 Hz
                counter = FREQUENCY;
    
                // check for master state (optional)
                check_master_state();
                check_slave_config_states();
    
    #ifdef MEASURE_TIMING
                // output timing stats
                printf("period     min:%10u(ns) | max:%10u(ns)\n",
                        period_min_ns, period_max_ns);
                printf("exec       min:%10u(ns) | max:%10u(ns)\n",
                        exec_min_ns, exec_max_ns);
                printf("latency    min:%10u(ns) | max:%10u(ns)\n",
                        latency_min_ns, latency_max_ns);
                printf("send       min:%10u(ns) | avg:%10lu(ns) | max:%10u(ns)\n",
                        send_min_ns, send_avg_time, send_max_ns);
                printf("read       min:%10u(ns) | avg:%10lu(ns) | max:%10u(ns)\n",
                        recv_min_ns, recv_avg_time, recv_max_ns);
                period_max_ns = 0;
                period_min_ns = 0xffffffff;
                exec_max_ns = 0;
                exec_min_ns = 0xffffffff;
                latency_max_ns = 0;
                latency_min_ns = 0xffffffff;
                send_max_ns = 0;
                send_min_ns = 0xffffffff;
                recv_max_ns = 0;
                recv_min_ns = 0xffffffff;
    #endif
    
                // calculate new process data
                blink = !blink;
            }
    
            // write process data
            EC_WRITE_U8(domain1_pd + off_dig_out, blink ? 0x66 : 0x99);
            EC_WRITE_U8(domain1_pd + off_counter_out, blink ? 0x00 : 0x02);
    
            if (sync_ref_counter) {
                sync_ref_counter--;
            } else {
                sync_ref_counter = 1; // sync every cycle
    
                clock_gettime(CLOCK_TO_USE, &time);
                ecrt_master_sync_reference_clock_to(master, TIMESPEC2NS(time));
            }
            ecrt_master_sync_slave_clocks(master);
    
            // send process data
            ecrt_domain_queue(domain1);
            clock_gettime(CLOCK_TO_USE, &startSendTime);
            ecrt_master_send(master);
            clock_gettime(CLOCK_TO_USE, &endSendTime);
            send_ns = DIFF_NS(startSendTime, endSendTime);
            if (send_ns > send_max_ns) {
                send_max_ns = send_ns;
            }
            if (send_ns < send_min_ns) {
                send_min_ns = send_ns;
            }
            total_send_time += send_ns;
            send_avg_time = total_send_time/cyclic_cnt;
    
    #ifdef MEASURE_TIMING
            clock_gettime(CLOCK_TO_USE, &endTime);
    #endif
        }
    }
    
    /****************************************************************************/
    
    int main(int argc, char **argv)
    {
        
    
        if (mlockall(MCL_CURRENT | MCL_FUTURE) == -1) {
            perror("mlockall failed");
            return -1;
        }
    
        master = ecrt_request_master(0);
        if (!master)
            return -1;
    
        domain1 = ecrt_master_create_domain(master);
        if (!domain1)
            return -1;
    
        // Create configuration for bus coupler
        sc = ecrt_master_slave_config(master, TISlaveDemo_Pos, Beckhoff_TI_AM243X);
        if (!sc)
            return -1;
    
        printf("Configuring PDOs...\n");
        if (ecrt_slave_config_pdos(sc, EC_END, slave_1_syncs)) {
            fprintf(stderr, "Failed to configure PDOs.\n");
            return -1;
        }
    
    
        if (ecrt_domain_reg_pdo_entry_list(domain1, domain1_regs)) {
            fprintf(stderr, "PDO entry registration failed!\n");
            return -1;
        }
    
    
        printf("Activating master...\n");
        if (ecrt_master_activate(master))
            return -1;
    
        if (!(domain1_pd = ecrt_domain_data(domain1))) {
            return -1;
        }
    
        /* Set priority */
    
        struct sched_param param = {};
        param.sched_priority = sched_get_priority_max(SCHED_FIFO);
    
        printf("Using priority %i.\n", param.sched_priority);
        if (sched_setscheduler(0, SCHED_FIFO, &param) == -1) {
            perror("sched_setscheduler failed");
        }
    
        printf("Starting cyclic function.\n");
        cyclic_task();
    
        return 0;
    }
    
    /****************************************************************************/
    

  • Is the ethercat protocol stack closed source? I think it is based on the lib library. If there is source code, I can debug it and find the problem more easily.

  • Hello Wang Tao,

    Yes. TI EtherCAT SubDevice stack is a closed source. Sharing the details about source code needs a special SLA (software license agreement with TI Legal review). For more information on this, kindly contact the TI sales team.

    I want to understand if the EtherCAT SubDevice stack example has the issue at your end. Could you please provide the feedback to the below query?

    Have you tried scanning AM243x based EtherCAT SubDevice flashed with Simple demo example with TwinCAT or Conformance Test Tool? Do you still see the same issue in this case as well? If yes, then please share the error logs in TwinCAT/CTT or screenshots. Make sure you have copied the correct ESI files to the tool.

    Kind Regards,

  • Hello Wang Tao,

    You could use the EtherCAT Beckhoff SSC demo from the SDK and steps to rebuild the example can be found at Steps to Run the Example. You could debug the issue at you end with this example.

    Kind Regards,

  • I followed the documentation but encountered some problems.

    1. Unable to scan the slave.
    First I decided that this might be a problem with the twincat tool because I did not capture the ecat message of the network card.

    2. I use SOEM mster stack, it seems to be fine.

    I think there is an incompatibility issue between am243 and igh stack. For example, a certain version is required.

    So I still think whether you can provide a tested igh demo and a specific version number.

  • Hello Wang Tao,

    I would request you to provide the additional details.

    1. Unable to scan the slave.
    First I decided that this might be a problem with the twincat tool because I did not capture the ecat message of the network card.

    Please make sure that the same SubDevice has not been added previously. Try to remove all the devices in TwinCAT and perform the rescanning. Kindly copy the ESI file from <ind_comms_sdk_am243x>\source\industrial_comms\ethercat_slave\beckhoff_stack\esi\am64x_am243x\TI_ESC.xml to TwinCAT.

    2. I use SOEM mster stack, it seems to be fine.

    I think there is an incompatibility issue between am243 and igh stack. For example, a certain version is required.

    Could you please share the complete wireshark logs with IgH master from Init to Op state?

    Kind Regards,

  • 1、I just installed the twincat software today and created a new project. I copy TI_ESC.XML to TwinCAT. I use simple_demo not beckhoff_ssc_demo.Because I can't download this software

    • To build this example, it is necessary to get the EtherCAT SubDevice Stack Code (SSC). Download EtherCAT stack version 5.13 from ETG website and extract it to a local folder. Please refer to "Application Note ET9300 (EtherCAT SubDevice Stack Code)" for more details on SSC.

    2、pcap

    igh.zip

    mastet log

    root@lubancat:/home/cat# ethercatctl start
    [28653.926713] ec_generic: Binding socket to interface 4 (eth1).
    root@lubancat:/home/cat#
    root@lubancat:/home/cat#
    root@lubancat:/home/cat# [28657.090384] EtherCAT ERROR 0-0: Reception of CoE SDO description response failed:

    root@lubancat:/home/cat# ./ec_dc_user_example
    Configuring PDOs...
    Activating master...
    Using priority 99.
    [28664.290590] EtherCAT ERROR 0-0: Reception of CoE upload response failed: No response.
    [28664.290612] EtherCAT ERROR 0-0: Failed to read number of mapped PDO entries.
    [28664.317263] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [28664.347036] EtherCAT ERROR 0-0: Reception of CoE upload response failed:
    [28664.347044] EtherCAT ERROR 0-0: Failed to read number of mapped PDO entries.
    [28664.377254] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [28664.407256] EtherCAT ERROR 0-0: Reception of CoE upload response failed: No response.
    [28664.407263] EtherCAT ERROR 0-0: Failed to read number of mapped PDO entries.
    [28664.437251] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [28664.470582] EtherCAT ERROR 0-0: Reception of CoE upload response failed: No response.
    [28664.470588] EtherCAT ERROR 0-0: Failed to read number of mapped PDO entries.
    [28664.500585] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [28664.556812] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).
    ^C
    [28669.489672] EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".

    mcu log

    State change: 0x2 -> 0x1 errorcode:0x0
    State change: 0x1 -> 0x2 errorcode:0x0
    State change: 0x2 -> 0x12 errorcode:0x1e
    State change: 0x12 -> 0x2 errorcode:0x0

  • Hello Wang Tao,

    I have updated the SM2 and SM3 default size to 8 bytes in Simple demo example and attached the binary here. Kindly use this binary for EtherCAT SubDevice and let us know it this resolves the issue.
    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/908/ecSubDevice.appimage.hs_5F00_fs

    Kind Regards,

  • Hi,

    I referred to this article to burn, but failed

    https://software-dl.ti.com/mcu-plus-sdk/esd/AM243X/11_00_00_15/exports/docs/api_guide_am243x/GETTING_STARTED_FLASH.html.

    PS C:\ti\ind_comms_sdk_am243x_11_00_00_08\mcu_plus_sdk\tools\boot> python uart_uniflash.py -p COM17 --cfg=sbl_prebuilt/am243x-lp/default_sbl_null.cfg
    
    Parsing config file ...
    Parsing config file ... SUCCESS. Found 2 command(s) !!!
    
    Executing command 1 of 2 ...
    Found flash writer ... sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs
    
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   1%|▏           | 4116/283739 [00:00<00:42, 6638.11bytes/s]send error: expected ACK; got b'\x18' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   2%|▏           | 5145/283739 [00:00<00:33, 8399.73bytes/s]send error: expected ACK; got b'\x18' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   2%|▎           | 6174/283739 [00:00<00:33, 8399.73bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   3%|▎           | 7203/283739 [00:02<02:12, 2081.84bytes/s]send error: expected ACK; got b'2' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   3%|▎           | 8232/283739 [00:02<02:12, 2081.84bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   3%|▍           | 9261/283739 [00:02<02:11, 2081.84bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   4%|▍          | 10290/283739 [00:02<01:16, 3574.65bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   4%|▍          | 11319/283739 [00:02<01:16, 3574.65bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   4%|▍          | 12348/283739 [00:03<00:59, 4548.59bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   5%|▌          | 13377/283739 [00:03<00:59, 4548.59bytes/s]send error: expected ACK; got b'0' for block 4
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   5%|▌          | 14406/283739 [00:03<00:48, 5586.73bytes/s]send error: expected ACK; got b'0' for block 4
    send error: NAK received 11 times, aborting.
    Sending sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs:   5%|▌          | 14408/283739 [00:03<00:48, 5586.73bytes/s]
    [ERROR] XMODEM send failed, no response OR incorrect response from EVM OR cancelled by user,
    Power cycle EVM and run this script again !!!
    PS C:\ti\ind_comms_sdk_am243x_11_00_00_08\mcu_plus_sdk\tools\boot>

    #-----------------------------------------------------------------------------#
    #                                                                             #
    #      DEFAULT CONFIGURATION FILE TO BE USED WITH THE FLASHWRITER SCRIPT      #
    #                                                                             #
    #-----------------------------------------------------------------------------#
    #
    # By default this config file,
    # - points to pre-built flash writer, and SOC init bootloader or SBL NULL bootloader for this LP
    # - The SBL NULL bootloader does below
    #   - Load sysfw and init sysfw by passing a "boardcfg"
    #   - power-ON and clock setup for the R5F and M4F CPUs.
    #   - reset and run all the CPUs in a "WFI" loop.
    #   - It does NOT boot any applicaiton binary
    # - SBL NULL is useful to init the SOC when the LP is powered ON,
    #   so that one can do connect CCS and load application from CCS without needing
    #   to run any DMSC load scripts
    # - This make the CCS development flow lot simpler as long as this one time flashing step is done.
    #
    
    # First point to sbl_uart_uniflash binary, which function's as a server to flash one or more files
    --flash-writer=sbl_prebuilt/am243x-lp/ecSubDevice.appimage.hs_fs
    
    # When sending bootloader make sure to flash at offset 0x0. ROM expects bootloader at offset 0x0
    --file=sbl_prebuilt/am243x-lp/sbl_null.release.hs_fs.tiimage --operation=flash --flash-offset=0x80000

    I have some questions.

    1. Does the data length cause this problem?

    2. Does my IGH Master code need to be modified?

    3. Can you provide a modification method? Can I modify it directly on the source code?

  • mcu log  

    02000000011a0000616d3634780000000000000048534653000002000000020002a6000000000000 b018658ad99dc903c8c9bfb27b12751099920a042ad1dfea7b7ba57369f15546de285edde6a7b39a 8bdc40a27b237f8fb1e57f245e80b929c1e28b024aa2ecc6ad0bc40b000000000000000000000000 00000000000000000000000000000000000000000000000000000000000000000000000000000000 0000000000000000355e49d037d910339db65a91cae3243dec16d20a33eb6f3042a55bba59aa4d05 CCCCCCCC

  • Hello Wang Tao,

    Please follow the below workaround to update the EEPROM in Simple demo.
    1. In ecSubDeviceSimple.c file, add the following line of code.

    EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true);       // Add this line
    error = (EC_API_EError_t)EC_API_SLV_init(pAppInstance_p->ptEcSlvApi); // Existing

    2. Change the macro EEPROM_MAGIC_KEY value to reinitialize the EEPROM after power up.

    Kind Regards,

  • Hi,

    I made a mistake before, and now it can be burned normally. Therefore, I did not follow this method.

    1. In ecSubDeviceSimple.c file, add the following line of code.

    This is the MCU log. Can I see if it is the program you sent me?

    DMSC Firmware Version 11.0.7--v11.00.07 (Fancy Rat)
    DMSC Firmware revision 0xb
    DMSC ABI revision 4.0

    KPI_DATA: [BOOTLOADER_PROFILE] Boot Media : NOR SPI FLASH
    KPI_DATA: [BOOTLOADER_PROFILE] Boot Media Clock : 100.000 MHz
    KPI_DATA: [BOOTLOADER_PROFILE] Boot Image Size : 275 KB
    KPI_DATA: [BOOTLOADER_PROFILE] Cores present :
    r5f0-0
    KPI_DATA: [BOOTLOADER PROFILE] SYSFW init : 11126us
    KPI_DATA: [BOOTLOADER PROFILE] System_init : 11710us
    KPI_DATA: [BOOTLOADER PROFILE] Drivers_open : 1644us
    KPI_DATA: [BOOTLOADER PROFILE] Board_driversOpen : 649629us
    KPI_DATA: [BOOTLOADER PROFILE] Sciclient Get Version : 9846us
    KPI_DATA: [BOOTLOADER PROFILE] CPU load : 73028us
    KPI_DATA: [BOOTLOADER PROFILE] SBL End : 3us
    KPI_DATA: [BOOTLOADER_PROFILE] SBL Total Time Taken : 756990us

    Image loading done, switching to application ...

    Local Implementation
    Pruicss max =3 selected PRU:3
    pRegPerm = 0x30082000, dram1=0x30082000, offset = 0x00000000, size = 0x00001400
    PRU ESC: Rev 0690 | Bld 0536 | INTC base: 0x300a0000 , id = 0x4e82a900
    INTC.HIDISR addr: 0x300a0038
    RxPDO created 0x1600: 0x7013ba30
    RxPDO created 0x1601: 0x7013bb38
    TxPDO created 0x1A00: 0x7013bbd0
    TxPDO created 0x1A01: 0x7013bcd8
    EC_SLV_INT_EEPEMU_prepare:652: Set CatSyncMan[1]:sa=0x1000, len=0x400, ctrl=0x26, ena=1
    EC_SLV_INT_EEPEMU_prepare:661: Set CatSyncMan[2]:sa=0x1400, len=0x400, ctrl=0x22, ena=1
    EC_SLV_INT_EEPEMU_prepare:670: Set CatSyncMan[3]:sa=0x1800, len=0xc00, ctrl=0x64, ena=1
    EC_SLV_INT_EEPEMU_prepare:687: Set CatSyncMan[4]:sa=0x2400, len=0xc00, ctrl=0x20, ena=1
    SM2 size is 8
    SM3 size is 8
    EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40
    Phy Reset: 0.28
    Phy Reset: 0.20
    Phy UnReset: 0.28
    Phy UnReset: 0.20
    Configure Phy bits: PhyAddr:3, LinPol:HIGH, PhyAddr:15, LinPol:HIGH, (0x0)
    DP83869 detected
    DP83869 detected
    PRU_PHY_detect:152 Phy 3 alive
    PRU_PHY_detect:152 Phy 15 alive
    Phy 3 : Disable RGMII mode
    Phy 3 : Disable GBit ANEG
    Phy 15 : Disable RGMII mode
    Phy 15 : Disable GBit ANEG
    PHY Disable Magnetics
    PHY Enable Magnetics
    TI EtherCAT Toolkit for AM243X.R5F - e000059dh / 54490026h
    Explicit Device ID : 0x 5

    ****EC SubDevice*********************************************************
    Numeric Version: 0x00020101
    Source Id: <de44f9db5ddd890eeea09db30217def4e3062ec9>
    ****HWAL*************************************************************
    Numeric Version: 0x00020100
    Friendly Version: <KB HWAL v00.02.01.00>
    Source Id: <3764cbbee02563e73129376ccac8d785bd6e2773>
    ****OSAL*************************************************************
    Numeric Version: 0x00010301
    Friendly Version: <KB OSAL v00.01.03.01>
    Source Id: <5e1dcc50bb40791bdb358cecc4e4fd35beca6d1e>
    *********************************************************************
    State change: 0x0 -> 0x1
    SSC_checkTimer:MaxD:9355400 (9)
    SSC_checkTimer:MaxET:8
    SSC_checkTimer:MaxD:11999180 (11)
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x4
    State change: 0x4 -> 0x14
    State change: 0x14 -> 0x4
    State change: 0x4 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x4
    State change: 0x4 -> 0x14
    State change: 0x14 -> 0x4
    State change: 0x4 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x4
    State change: 0x4 -> 0x14

    master log

    [ 527.550137] EtherCAT DEBUG 0-0: Clearing sync manager configurations...
    [ 527.550275] EtherCAT DEBUG 0-0: Clearing DC assignment...
    [ 527.550411] EtherCAT DEBUG 0-0: Configuring mailbox sync managers...
    [ 527.550417] EtherCAT DEBUG 0-0: SM0: Addr 0x1000, Size 1024, Ctrl 0x26, En 1
    [ 527.550421] EtherCAT DEBUG 0-0: SM1: Addr 0x1400, Size 1024, Ctrl 0x22, En 1
    [ 527.550556] EtherCAT DEBUG 0-0: Assigning SII access to PDI.
    [ 527.560047] EtherCAT DEBUG 0-0: Now in PREOP.
    [ 527.560052] EtherCAT DEBUG 0-0: Assigning SII access back to EtherCAT.
    [ 527.560191] EtherCAT DEBUG 0-0: SM2: Addr 0x1800, Size 8, Ctrl 0x64, En 1
    [ 527.560195] EtherCAT DEBUG 0-0: SM3: Addr 0x2400, Size 8, Ctrl 0x20, En 1
    [ 527.562299] EtherCAT DEBUG 0-0: Now in SAFEOP.
    [ 527.792550] EtherCAT WARNING: Datagram 00000000df0b7bf6 (master-fsm) was SKIPPED 1 time.
    root@lubancat:/home/cat# [ 532.559260] EtherCAT ERROR 0-0: Timeout while setting state OP.

    root@lubancat:/home/cat#
    root@lubancat:/home/cat# ethercat slaves
    0 0:0 SAFEOP+ERROR E TI EtherCAT Toolkit for AM243X.R5F
    root@lubancat:/home/cat#

    Unfortunately, I still cannot enter the OP state, but the error message seems to be a little different from the original one. The mcu is 0x14, and the master shows that it has timed out from switching to OP.

  • Unfortunately, I still cannot enter the OP state, but the error message seems to be a little different from the original one.

    Please share wireshark logs along with master logs while reporting issues

  • Hi

    ecat.zip

    master

    [ 7914.633491] EtherCAT: Successfully requested master 0.
    [ 7914.633615] EtherCAT 0: Domain0: Logical address 0x00000000, 8 byte, expected working counter 1.
    [ 7914.633620] EtherCAT 0: Datagram domain0-0-main: Logical offset 0x00000000, 8 byte, type LWR.
    [ 7914.633648] EtherCAT 0: Master thread exited.
    [ 7914.633655] EtherCAT 0: Stopping EoE thread.
    [ 7914.633671] EtherCAT 0: EoE thread exited.
    [ 7914.633674] EtherCAT 0: Starting EoE thread.
    [ 7914.633753] EtherCAT 0: Starting EtherCAT-OP thread.
    [ 7914.633810] EtherCAT WARNING 0: No application time received up to now, but master already active.
    [ 7914.667762] EtherCAT ERROR 0-0: AL status message 0x001B: "Sync manager watchdog".
    [ 7914.694420] EtherCAT 0-0: Acknowledged state SAFEOP.
    [ 7919.897737] EtherCAT ERROR 0-0: Timeout while setting state OP.
    [ 7995.969033] EtherCAT 0: Releasing master...
    [ 7995.969065] EtherCAT 0: Master thread exited.
    [ 7995.969068] EtherCAT 0: Stopping EoE thread.
    [ 7995.969083] EtherCAT 0: EoE thread exited.
    [ 7995.969101] EtherCAT 0: Starting EoE thread.
    [ 7995.969173] EtherCAT 0: Starting EtherCAT-IDLE thread.
    [ 7995.969226] EtherCAT 0: Released.
    [ 7995.984541] EtherCAT ERROR 0-0: AL status message 0x001B: "Sync manager watchdog".
    [ 7995.984840] EtherCAT 0-0: Acknowledged state SAFEOP.
    [ 8000.994409] EtherCAT ERROR 0-0: Timeout while setting state OP.
    [ 8001.001062] EtherCAT 0: Slave states on main device: SAFEOP.
    [ 8004.201056] EtherCAT 0: Slave states on main device: SAFEOP + ERROR.

    mcu

    State change: 0x4 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x4
    State change: 0x4 -> 0x14
    State change: 0x14 -> 0x4
    State change: 0x4 -> 0x1
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x4
    State change: 0x4 -> 0x14

  • Hi,

    Is there any progress?

  • Hi Wang,

    Can you just check the MII_RT_TXCFG0 (0x300B2010) and MII_RT_TXCFG1 (0x300B2014) and make sure TX_START_DELAY is increased to 0x98:

    For SOEM and IgH MainDevice operation, the start delay is to be increased and this is handled dynamically via the EtherCAT PRU Firmware. There may be that this time is not increased dynamically for some reason in IgH network.

    Do let me know the value observed in your setup.

    Also, we're analyzing the wireshark logs for any unintended behavior/configuration.

    Regards,
    Aaron

  • Hi

    How can I view these values? Is there any reference code?

  • Is this statistic correct?

  • Our project is very urgent. Can you compile all your doubts into a package and send it to me so that I can verify it?

  • Hi Wang,

    Is this statistic correct?
    • Yes it is correct. I see that the TX_START_DELAY is 0x48 (which equals to 360ns) for port0 and port1.
    • The expectation is that while in SAFEOP, based on the number of FMMU entries (Read, Write, Read+Write), the delay should increase based on couple of internal checks (in the case of SOEM or IgH or if more than 4 SyncManagers arebeing used).

    Make sure during SAFEOP, the TX_START_DELAY is increased to 0x98 (760ns). If this is not increased, then recommend to increase the TX_START_DELAY manually by updating the following ESC Vendor Specific Register for Port0 to 0x98:

    • Physical Address: 0x30090E10

    Post this, rebuild the application, verify 0xE10 register is updated to 0x98 and then try running IgH.

    Regards,
    Aaron

  • Hi

    I made the following changes.I wasn't sure where to add it, so I set it to 0x98 on the first state switch.

    From the log, we can see that the first switch is 0x48, and the second switch is 0x98.

    *********************************************************************
    State change: 0x0 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00000500 MII_RT_TXCFG1=0x00000000 TX_START_DELAY:48
    SSC_checkTimer:MaxD:9789620 (9)
    SSC_checkTimer:MaxET:54
    SSC_checkTimer:MaxD:12001665 (12)
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x2 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    SSC_checkTimer:MaxD:15625875 (15)
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x2 -> 0x12 errorcode:0x1e MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x12 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98

    master log

    root@lubancat:/home/cat# [ 577.225019] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).
    [ 577.225168] EtherCAT ERROR 0-0: AL status message 0x001E: "Invalid input configuration".

    Still doesn't seem to work properly.

    At this time, start soem and the slave can work normally

    State change: 0x2 -> 0x12 errorcode:0x1e MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x12 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x2 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    State change: 0x2 -> 0x4 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98
    SSC_checkTimer:MaxD:-390028 (4294)
    State change: 0x4 -> 0x8 errorcode:0x0 MII_RT_TXCFG0 = 0x00480500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:98

    My question is that when soem starts, the value of the register is the same as that of igh. If it is a problem with the register value, why one works and the other doesn't?

  • Hi

    I have updated the SM2 and SM3 default size to 8 bytes in Simple demo example and attached the binary here. Kindly use this binary for EtherCAT SubDevice and let us know it this resolves the issue.
    ecSubDevice.appimage.hs_fs

    What parts of the program you sent me last time were modified? Because I found that the one you gave me failed to enter safeop, and the one I compiled myself failed to enter preop. So I want to add your modifications to my own project to see if there is any improvement.

  • Hello Wang Tao,

    Please follow the below workaround to update the EEPROM in Simple demo.
    1. In ecSubDeviceSimple.c file, add the following line of code.

    Fullscreen
    1
    2
    EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true); // Add this line
    error = (EC_API_EError_t)EC_API_SLV_init(pAppInstance_p->ptEcSlvApi); // Existing
    XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

    2. Change the macro EEPROM_MAGIC_KEY value to reinitialize the EEPROM after power up.

    Kind Regards,

  • Hi,

    In my project, there is no ecSubDeviceSimple.c file.

  • Hi Wang Tao,

    If you are not using the latest SDK then please look for ecSlaveSimple.c file.

    Kind Regards,

  • Hi,

    Do I just need to change EEPROM_MAGIC_KEY and then compile and burn it?

  • Hi Wang Tao,

    Yes. You can find the macro EEPROM_MAGIC_KEY in project.h file.

    Kind Regards,

  • Hi

    I changed the macro definition and tried it twice, but the phenomenon did not change.

  • Hi,

    The program you sent me will have the following printouts, but I didn't compile it myself. Is this the printout you added? If you did, please tell me how to add it and confirm what my program is.

    EC_SLV_INT_EEPEMU_prepare:687: Set CatSyncMan[4]:sa=0x2400, len=0xc00, ctrl=0x20, ena=1
    SM2 size is 8
    SM3 size is 8
    EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40

  • Hello Wang Tao,
    The print statements were added in the stack for debug purposes. You can read the SM2 and SM3 size from the EEPROM. Please refer the screenshot below. You can read the EEPROM contents in the EtherCAT Conformance Test Tool (CTT).


    Kind Regards,

  • Hi,

    This tool requires membership to use.

    View through the command

    your image:size 8

    my image: size 0

    But when I use soem to read the information, it shows 8.


    So I still suspect that there is a problem with igh and slave, which leads to the error in size reading.
    1、Can you test it based on igh, because guessing verification is less efficient.
    2、Did you change more than one place in the program you sent me, because using igh  on your program, the reading is 8, which is better than compiling it myself.

  • HI

    I tried several times, and the biggest difference between our programs is the size, which leads to differences in the subsequent processes. I think we can focus on why the program I compiled reads 0.

  • Hi Wang Tao,

    Those are the only changes required at one place as specified before.

    Kind Regards,

  • Hi

    I am not using the same project as you, so the modifications are different. I am using motor_control_sdk_am243x_09_02_00_11\ind_comms_sdk\examples\industrial_comms\ethercat_slave_demo.

    Can you try this project?

  • Hi

    I debugged the source code and found that changing the magic value can indeed cause the eeprom to be rewritten. I printed out the value.

    1、Can you tell what the size is?

    2、I think there should be a default value in the software. Is this written in the library? So I didn't find it.

    MAIN_Cortex_R5_0_0: write default value....
    
    MAIN_Cortex_R5_0_0: 80 c e0 88 e8 3 0 0 0 0 0 0 0 0 8b 0 9d 5 0 e0 25 0 49 54 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 0 1 0 12 0 1 0 10 0 4 0 14 0 4 f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
    MAIN_Cortex_R5_0_0: 0 0 0 f 0 1 0 a 0 27 0 4 22 54 49 20 45 74 68 65 72 43 41 54 20 54 6f 6f 6c 6b 69 74 20 66 6f 72 20 41 4d 32 34 33 58 2e 52 35 46 10 45 74 68 65 72 43 41 54 20 54 6f 6f 6c 6b 69 74 b 53 4d 2d 53 79 6e 63 68 72 6f 6e b 44 43 2d 53 79 6e 63 68 72 6f 6e 0 1e 
    MAIN_Cortex_R5_0_0: 0 10 0 2 0 1 1 0 3b 1 1 0 0 0 4 0 0 1 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 0 2 0 1 2 3 ff 29 0 10 0 0 10 0 4 26 0 1 1 0 14 0 4 22 0 1 2 0 18 0 0 64 0 1 3 0 24 0 0 20 0 1 4 3c 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
    MAIN_Cortex_R5_0_0:  0 0 3 1 0 4 4 0 0 0 0 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff f
    MAIN_Cortex_R5_0_0: f ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
    MAIN_Cortex_R5_0_0:  ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
    MAIN_Cortex_R5_0_0: ff ff ff ff ff ff ff write default value done

  • Hi Wang Tao,

    1. As per your log, SM2 size = 0x00 and SM3 size = 0x00.

    2. Yes. The default SM2 and SM3 size will be written in the stack.

    Have you added this statement EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true); at the specified location?

    I tested with the same subdevice stack example version as yours.

    ****EC Slave*********************************************************
    Numeric Version: 0x00020003

    Kind Regards,

  • Hi,

    Have you added this statement EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true); at the specified location?

    I added a line here and changed the value of magic. Now igh reads size as 8.

    But the result is still the same, no improvement.

    master log

    [ 976.693184] EtherCAT ERROR 0-0: Reception of CoE download response failed:
    [ 976.746513] EtherCAT ERROR 0-0: Reception of CoE download response failed:
    [ 976.773403] EtherCAT ERROR 0-0: Reception of CoE download response failed: No response.
    [ 976.799844] EtherCAT ERROR 0-0: Reception of CoE download response failed:
    [ 976.826521] EtherCAT ERROR 0-0: Reception of CoE download response failed:
    [ 976.879620] EtherCAT ERROR 0-0: Failed to set SAFEOP state, slave refused state change (PREOP + ERROR).

    mcu log

    State change: 0x14 -> 0x4 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x4 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x2 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    SSC_checkTimer:MaxD:18638575 (18)
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    **************************************
    New assignments for SyncManager 2:
    New assignments for SyncManager 3:
    **************************************
    State change: 0x2 -> 0x12 errorcode:0x1e MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    SSC_checkTimer:MaxD:21519900 (21)
    State change: 0x12 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x2 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    **************************************
    New assignments for SyncManager 2:
    New assignments for SyncManager 3:
    **************************************
    State change: 0x2 -> 0x12 errorcode:0x1e MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    SSC_checkTimer:MaxD:22318495 (22)
    State change: 0x12 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x2 -> 0x1 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98
    State change: 0x1 -> 0x2 errorcode:0x0 MII_RT_TXCFG0 = 0x00980500 MII_RT_TXCFG1=0x00980401 TX_START_DELAY:0x98 TX_START_DELAY:0x98

    Your image does not have the following log:

    **************************************
    New assignments for SyncManager 2:
    New assignments for SyncManager 3:
    **************************************

    In addition, your image fails to enter op, and my image fails to enter safeop

  • Hi

    But the image you sent me is

    ****EC SubDevice*********************************************************
    Numeric Version: 0x00020101
    Source Id: <de44f9db5ddd890eeea09db30217def4e3062ec9>
    ****HWAL*************************************************************

  • HI

    AM243x INDUSTRIAL COMMUNICATIONS SDK  11.00.00
    I want to try the latest SDK, but after burning, the program always fails to start, stuck here, the light on the board does not flash, and the system cannot start normally. What is the reason? I also mentioned it during the discussion, but did not get a reply.

    Sorry for replying three times in a row, but I hope you can reply to each of my questions individually so that I can get more information.

  • Hello Wang Tao,

    **************************************
    New assignments for SyncManager 2:
    New assignments for SyncManager 3:
    **************************************

    Looks like your IGH master is trying to reconfigure PDO assignments and removing the default assignments to 0x1C12 and 0x1C13. Hence, there are no output/input process data. In your subdevice example, you have enabled the PDO re-assignments, and you see above debug messages. In the binary which I had shared you, the PDO re-assignments are disabled. Hence you do not see these debug messages. Why do you remove the default PDO assignments and no new PDOs assigned again?

    ****EC SubDevice*********************************************************
    Numeric Version: 0x00020101

    I mentioned that I had also tested the subdevice example version 2.00.03 you are building locally. I had shared the subdevice example version 2.01.01 binary with default SM2/SM3 size set to 8, for testing purpose.

    Can you share the complete logs of ICSDK 11.00.00 subdevice example which is not working?

    Kind Regards, 

  • Hi

    1、

    Why do you remove the default PDO assignments and no new PDOs assigned again?
       
    I followed the method you said, and then this log appeared
    EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true); //add line
        error = (EC_API_EError_t)EC_API_SLV_init(pAppInstance_p->ptEcSlvApi);

    Do you mean to burn it after modification, then comment out this line, and then compile and burn it?

    2、There are no more logs. This is the last log EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40

    Image loading done, switching to application ...
    
    Local Implementation
    Pruicss  max =3 selected PRU:3
    pRegPerm = 0x30082000, dram1=0x30082000, offset = 0x00000000, size = 0x00001400
    PRU ESC: Rev 0690 | Bld 0536 | INTC base: 0x300a0000 , id = 0x4e82a900
    INTC.HIDISR addr: 0x300a0038
    RxPDO created 0x1600: 0x7013ba30
    RxPDO created 0x1601: 0x7013bb38
    TxPDO created 0x1A00: 0x7013bbd0
    TxPDO created 0x1A01: 0x7013bcd8
    EC_SLV_INT_EEPEMU_prepare:652: Set CatSyncMan[1]:sa=0x1000, len=0x400, ctrl=0x26, ena=1
    EC_SLV_INT_EEPEMU_prepare:661: Set CatSyncMan[2]:sa=0x1400, len=0x400, ctrl=0x22, ena=1
    EC_SLV_INT_EEPEMU_prepare:670: Set CatSyncMan[3]:sa=0x1800, len=0xc00, ctrl=0x64, ena=1
    EC_SLV_INT_EEPEMU_prepare:687: Set CatSyncMan[4]:sa=0x2400, len=0xc00, ctrl=0x20, ena=1
    SM2 size is 8
    SM3 size is 8
    EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40
    Phy Reset: 0.28
    Phy Reset: 0.20
    Phy UnReset: 0.28
    Phy UnReset: 0.20
    Configure Phy bits: PhyAddr:3, LinPol:HIGH, PhyAddr:15, LinPol:HIGH, (0x0)
    DP83869 detected
    DP83869 detected
    PRU_PHY_detect:152 Phy 3 alive
    PRU_PHY_detect:152 Phy 15 alive
    Phy 3 : Disable RGMII mode
    Phy 3 : Disable GBit ANEG
    Phy 15 : Disable RGMII mode
    Phy 15 : Disable GBit ANEG
    PHY Disable Magnetics
    PHY Enable Magnetics
    TI EtherCAT Toolkit for AM243X.R5F - e000059dh / 54490026h
    Explicit Device ID : 0x   5
    
    ****EC SubDevice*********************************************************
    Numeric Version: 0x00020101
    Source Id: <de44f9db5ddd890eeea09db30217def4e3062ec9>
    ****HWAL*************************************************************
    Numeric Version: 0x00020100
    Friendly Version: <KB HWAL v00.02.01.00>
    Source Id: <3764cbbee02563e73129376ccac8d785bd6e2773>
    ****OSAL*************************************************************
    Numeric Version: 0x00010301
    Friendly Version: <KB OSAL v00.01.03.01>
    Source Id: <5e1dcc50bb40791bdb358cecc4e4fd35beca6d1e>
    *********************************************************************
    State change: 0x0 -> 0x1
    SSC_checkTimer:MaxD:9346200 (9)
    SSC_checkTimer:MaxET:8
    SSC_checkTimer:MaxD:11999475 (11)
    State change: 0x1 -> 0x2
    State change: 0x2 -> 0x1
    State change: 0x1 -> 0x2
    
    Local Implementation
    Pruicss  max =3 selected PRU:3
    Phy Reset: 0.28
    Phy Reset: 0.20
    pRegPerm = 0x30082000, dram1=0x30082000, offset = 0x00000000, size = 0x00001400
    PRU ESC: Rev 0690 | Bld 0536 | INTC base: 0x300a0000 , id = 0x4e82a900
    INTC.HIDISR addr: 0x300a0038
    RxPDO created 0x1600: 0x70139da0
    RxPDO created 0x1601: 0x70139ea8
    TxPDO created 0x1A00: 0x70139f40
    TxPDO created 0x1A01: 0x7013a048
    EC_SLV_INT_EEPEMU_prepare:652: Set CatSyncMan[1]:sa=0x1000, len=0x400, ctrl=0x26, ena=1
    EC_SLV_INT_EEPEMU_prepare:661: Set CatSyncMan[2]:sa=0x1400, len=0x400, ctrl=0x22, ena=1
    EC_SLV_INT_EEPEMU_prepare:670: Set CatSyncMan[3]:sa=0x1800, len=0xc00, ctrl=0x64, ena=1
    EC_SLV_INT_EEPEMU_prepare:687: Set CatSyncMan[4]:sa=0x2400, len=0xc00, ctrl=0x20, ena=1
    EC_SLV_APP_SS_populateDescriptionObjectValues:1649 PDO Out Len: 0x40
    
    

  • Hi Wang Tao,

    Why do you remove the default PDO assignments and no new PDOs assigned again?

    This is with respect to IGH master code.  Why do your IGH master code removes the default PDO assignments and no new PDO assignments after that? Is this intentional?

    I tested the EtherCAT Simple demo from ICSDK 11.00.00.08, and it works fine. I could not be able to reproduce the issue at my end.

    Kind Regards,

  • Hi

    1、If I comment out this line, there will be no log. At the same time, the SM size is 8, which seems to be correct.

    //EC_API_SLV_PDO_setAssignment(pAppInstance_p->ptEcSlvApi, true); //add line
        error = (EC_API_EError_t)EC_API_SLV_init(pAppInstance_p->ptEcSlvApi);
    2、
    The same master program, why can your image enter safeop, but mine can't? There are two solutions now.
    1. I use your image to test, and then find out why it fails to enter op. I remember I have sent you the captured package before.
    2. Find out the difference between us, why can't my program enter safeop.
    Which solution do you think we should focus on first?