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AM2634: I2C Peripheral Behavior Varies with Task Priority

Part Number: AM2634

Tool/software:

Dear TI Support,

We are experiencing an unexpected behavior with the I2C peripheral on the AM2634 device. Specifically, we have observed that the I2C waveform changes significantly depending on the priority of the task executing the transaction.

Here is the code snippet we are using:

/* Set default transaction parameters */

I2C_Transaction_init(&i2cTransaction);

/* Override with required transaction parameters */

i2cTransaction.writeBuf     = outdata;

i2cTransaction.writeCount   = length;

i2cTransaction.targetAddress = slaveAddress;

i2cTransaction.timeout = I2C_TIMEOUT_US;

// Write data

status = I2C_transfer(i2cHandle, &i2cTransaction);

We have recorded two oscilloscope captures for i2c data and clock (attached as videos) showing the following:

  • When the task has high priority, the waveforms are "almost" consistent and repeatable.
  • When the task has low priority, the waveforms vary significantly, as if the transfer is being interrupted or delayed.

This raises a few questions:

  1. Why is the I2C transfer affected by the task priority? Shouldn't the peripheral handle the entire transfer autonomously once initiated?
  2. Is the “fragmented” waveform observed in the low-priority case compliant with the I2C standard?
  3. Could this behavior be causing the I2C slave device to freeze, as we have observed in some cases?

We would appreciate your technical insight into this issue and any suggestions for resolving it.

Thank you for your support.

Alessandro Pacifici

  • Hi Alessandro,

    Let me try to reproduce this issue on my end. I am not aware of any such issue on top of my head.

    1. Could this behavior be causing the I2C slave device to freeze, as we have observed in some cases?

    Yes this is possible. If the Slave device expects a constant connection and no clock stretching, it might fail/freeze.

    Also, can you help me with the I2C Addresses being used (not that it directly matters, but just want to confirm if no two addresses are being shared on the I2C bus right?)

    Regards,
    Shaunak

  • The slave device address is 0x51 and this is the only device on this i2c bus.

    Regards

  • Hi Shaunak,

    I just wanted to follow up and ask if there have been any updates regarding the issue. Were you able to reproduce the behavior on your end?

    Please let me know if you need any additional information from my side.

    Best regards,
    Alessandro

  • Hi Alessandro,

    Apologies I've been busy with some on-going debugs and could not look into it earlier, I'm yet to reproduce the issue and have a deeper look. I'll try to dig deeper tomorrow as soon as i'm back in office.

    At a very high level, I believe the I2C Transfer on AM26x, has a lot of dependency on the R5F CPU for being called, is being CPU starved and thus in case of low priority task it does not behave well. While the I2C controller is actually responsible for doing the transfer, the driver is very CPU sensitive and thus delay between bytes violates the slave expectations and we see slave disconnected/freezing on the line.

    Maybe one thing i'll have to check here is that, is the behaviour same in Callback mode as well as interrupt mode? This is definitely something that can be overcome by DMA.

    Another point is, We do not have the DMA integrated in the Software I2C driver yet (HW supports it), once we have it, there will be less dependency on the R5F CPU. The hardware does not fully transfer all the data and R5F has to be involved for data movement, servicing interrupts etc (for example for every byte sent or received, the CPU has to be involved, so the I2C without DMA right now is almost Byte-serviced by the CPU)

    Regards,
    Shaunak

  • Hi Shaunak,

    Thank you again for your detailed response.

    Regarding the interrupt mode: that was actually our initial choice, but we had to discard it due to much more frequent issues. In our tests, the I2C frames were often corrupted, making communication unreliable. We also noticed that other users have reported similar problems with the interrupt mode, such as in this thread:
    AM2634-Q1: Issue reading full 7 bytes from DS1307 RTC using I2C in interrupt mode on AM2634

    To better understand your explanation, I have a couple of questions:

    • Is the I2C clock also managed by software?
    • Is the I2C peripheral a true hardware peripheral, or is it a software emulation using GPIOs controlled by software?

    Also, you mentioned that DMA could help overcome these issues. Could you please share more details about the DMA mode? Specifically:

    • How would it change the current behavior?
    • Do you have any estimate on when DMA support might be available in the software driver?

    Finally, are there any recommended workarounds or alternative approaches we could consider in the meantime to avoid this issue?

    Thanks again for your support!

    Best regards,
    Alessandro

  • Hi Alessandro,

    Also, you mentioned that DMA could help overcome these issues. Could you please share more details about the DMA mode? Specifically:

    • How would it change the current behavior?
    • Do you have any estimate on when DMA support might be available in the software driver?

    - In DMA mode, there is less expected involvement of CPU, which means regardless of the task priority executing I2C, it will not have jitters
    - I'll confirm with the DEV team once on the SDK version for the I2C DMA driver

    To better understand your explanation, I have a couple of questions:

    • Is the I2C clock also managed by software?
    • Is the I2C peripheral a true hardware peripheral, or is it a software emulation using GPIOs controlled by software?

    As far as I know, it is a true peripheral and not a GPIO emulation. The clock is configured once and then the HW should control it. Let me loop in some HW experts.

    Regards,
    Shaunak

  • I did confirm with our HW experts,

    1. I2C clock is configured in SW once and not continuously controlled by SW

    2. It is a true I2C HW and not GPIO emulation

    Regards,
    Shaunak

  • Hi Shaunak,

    Thanks for confirming that the I2C peripheral is true hardware and that the clock is configured once in software.

    Given that, I’m still puzzled by the behavior we’re observing:
    Why does the I2C clock waveform appear to change during a transaction depending on the task priority?
    This suggests that something in the system—possibly the CPU load or task scheduling—is still affecting the timing of the I2C signals, even though the clock should be hardware-driven.

    This behavior is critical for us, as it seems to be the root cause of the communication issues and slave freezes we’re experiencing. Could this be due to the CPU being too involved in byte-by-byte transfers, as you mentioned earlier?

    How can we fix or work around this behavior in the current software stack?
    We’re open to suggestions—whether it’s using a different transfer mode, or implementing a workaround until DMA support becomes available.

    Also, any update or timeline on when DMA support might be integrated into the I2C driver would be very helpful for our planning.

    Thanks again for your support—we really appreciate your insights and help in resolving this.

    Best regards,
    Alessandro

  • Hi Alessandro,

    Our expert is OOO, please expect a response by mid next week.

  • Hi Alessandro,

    Why does the I2C clock waveform appear to change during a transaction depending on the task priority?

    The I2C transaction is interrupted or block by the task with higher priority, but the I2C clock (SCL) frequency (for example 400KHz, or 100KHz) should not be changed unless it is intentionally reconfigured. I will run a test to check how the SCL changes.

    Could this be due to the CPU being too involved in byte-by-byte transfers, as you mentioned earlier?

    You are correct. It seems to me that the I2C takes much bandwidth. If your application is not sending or receiving much data, you can configure the task a low priority, so it doesn't starve the more important tasks while the I2C transactions are in progress.

    How can we fix or work around this behavior in the current software stack?

    If the I2C transactions in your application must not be blocked, please configure I2C task as higher priority. Another way is to suspend the tasks who may interrupt I2C transactions.

    Whenever a task is suspended, it will stay in the blocked state until it is resumed again. 

    Also, any update or timeline on when DMA support might be integrated into the I2C driver would be very helpful for our planning.
  • Hi Alessandro,

    Is this a custom board or the TI Launchpad/control-card?

    Regards,
    Shaunak

  • It is a custom board.

    Regards

    Alessandro

  • Hi Alessandro,

    Would it be possible to have a call today? I'll share the meeting invite over email. Let me know when you will be available?

    Regards,
    Shaunak

  • Sure! We are available till 17.00 CEST.

  • Perfect, let me share the invite over email to you, please forward it to all the folks necessary, 

    Also, can you share the schematics of your custom board to me over email? Has the schematics been reviewed by the TI team before?

    Regards,
    Shaunak

  • Hi Alessandro,

    Closing this thread on E2E since we are having conversations over email. You can re-open the thread if needed. The team is looking into the I2C DMA mode implementation and will share the estimated effort and further comments over email in 1-2 days.

    Regards,
    Shaunak