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AM2612: What is difference between VIM0 and VIM1 ?

Part Number: AM2612

Tool/software:

Hi,

My customer has some questions about VIM (Vectored Interrupt Manager). Could you help to answer their questions below ?

1. Could you tell them what is difference between VIM0 and VIM1 ?

2. Are these the same as VIM0-0 and VIM0-1 shown in the Figure 3-3 in the TRM ?

3. Could you tell them a use case how to use these two VIM0/1 differently ?

 

Thanks and regards,

Hideaki

  • Hi Hideaki

    1. Could you tell them what is difference between VIM0 and VIM1 ?



    The device has two Real-time mcununits (R5FSS0 and R5FSS1). Each of these R5F Subsystems contains a Dual-R5F Cluster and its own Vectored Interrupt Manager (VIM) module. Therefore, VIM0 refers to the VIM associated with R5FSS0, and VIM1 refers to the VIM associated with R5FSS1. These are independent interrupt managers for their respective R5F Subsystems.


    2. Are these the same as VIM0-0 and VIM0-1 shown in the Figure 3-3 in the TRM ?

    No, they are not the same.


    Figure 3-3 shows "R5FSS0-0" and "R5FSS0-1" connecting to "VIM interconnect" blocks, with outputs labeled "VIM0-0" and "VIM0-1".
    This indicates that VIM0-0 and VIM0-1 are specific interrupt outputs or paths originating from the VIM associated with the individual R5F cores within R5FSS0 (the first R5F Subsystem). The "VIM0" in the context of question 1 refers to the entire VIM module for R5FSS0, which would include the handling of interrupts from both R5FSS0-0 and R5FSS0-1.

    3. Could you tell them a use case how to use these two VIM0/1 differently ?



    A common use case involves distributing interrupt loads in multi-core applications:

    VIM0 (for R5FSS0): Can handle high-priority, safety-critical, or real-time sensitive interrupts (e.g., motor control feedback, safety monitoring, critical communication).
    VIM1 (for R5FSS1): Can manage lower-priority or general-purpose interrupts (e.g., communication, user interface, diagnostics) to prevent interference with critical tasks handled by R5FSS0.

    This separation enhances system determinism, responsiveness, and simplifies software design by isolating interrupt handling responsibilities across the R5F Subsystems.

    Regards,
    Akshit