AM263P4-Q1: The xSPI (8D) SFDP Boot Loader operation and process is not documented anywhere in the TRM

Sanith goud Kothuri

Part Number: AM263P4-Q1

Tool/software:

We are working on the AM263Px SoC and are trying to boot from OSPI flash using the XIP (eXecute In Place) feature. To enable this, the recommended boot mode is xSPI 8D SFDP. However, after reviewing Section 5.4 "Boot Modes" of the TRM, we could not find detailed information regarding the xSPI boot loader operation and process. While there is some documentation about OSPI 8S boot, it does not support XIP.

We would like to understand the xSPI boot mode and process in depth. Specifically, if we configure the boot switches to select xSPI boot mode:

What does the ROM Bootloader (RBL) do in order to execute the image from OSPI flash?
If we implement secure boot using a Secondary Bootloader (SBL), how does control transfer from the RBL to the SBL, and how is the SBL executed?

Regarding the SBL, we referred to Section 5.7.7 "R5 SBL Hand-off". We would like to confirm whether this hand-off mechanism is also applicable to xSPI 8D boot mode. Specifically, how is the SBL executed in XIP mode?
Does the entire SBL get copied into on-chip RAM and then executed, or is the SBL itself executed directly from flash using XIP, without being copied to RAM?

3) If my core is running at 300Mhz and if i use XIP which runs at OSPI flash speed which is 133Mhz, will there be any conflicts in time while executing instructions from OSPI flash (any timing related issues for instruction execution)

2 months ago

0 Nilabh Anand 2 months ago

TI__Mastermind 45084 points

SBL execution in XIP is not possible in any of the mode. ROM needs SBL to be run from RAM.

0 Nilabh Anand 2 months ago in reply to Nilabh Anand

TI__Mastermind 45084 points

Please refer to JEDEC standard to learn about the xSPI protocol

https://www.jedec.org/standards-documents/docs/jesd251c

Sanith goud Kothuri said:
. Specifically, how is the SBL executed in XIP mode?

This is not supported.

Sanith goud Kothuri said:
3) If my core is running at 300Mhz and if i use XIP which runs at OSPI flash speed which is 133Mhz, will there be any conflicts in time while executing instructions from OSPI flash (any timing related issues for instruction execution)

300Mhz is not a supported configuration for which we claim support for.

0 Sanith goud Kothuri 2 months ago in reply to Nilabh Anand

Prodigy 85 points

Do you mean that we can't generate 300 MHz by configuring the PLL and its registers?

0 Sanith goud Kothuri 2 months ago in reply to Nilabh Anand

Prodigy 85 points

Is there any way to obtain the RBL code that TI has programmed into the MCU or at least RBL code flow chart to analyze what RBL does in xSPI boot mode

0 Nilabh Anand 2 months ago in reply to Sanith goud Kothuri

TI__Mastermind 45084 points

Sanith goud Kothuri said:
Is there any way to obtain the RBL code that TI has programmed into the MCU or at least RBL code flow chart to analyze what RBL does in xSPI boot mode

You can read about the high level flow in TRM Boot section. I belive that has sufficient details.

0 Nilabh Anand 2 months ago in reply to Sanith goud Kothuri

TI__Mastermind 45084 points

Sanith goud Kothuri said:
Do you mean that we can't generate 300 MHz by configuring the PLL and its registers?

No, the SOC timing closure is done for 400Mhz

0 Sanith goud Kothuri 2 months ago in reply to Nilabh Anand

Prodigy 85 points

Ok thanks for the info.
If my SoC is running at 400 MHz and if I use XIP to execute instructions from OSPI flash running at 133 MHz, will there be any timing-related issues? Or to ensure smooth operation, do I need to apply any specific settings or configurations?

0 Sanith goud Kothuri 2 months ago in reply to Sanith goud Kothuri

Prodigy 85 points

Another question: In boot modes, what is the exact difference between OSPI (8S) boot mode and xSPI (8D) boot mode? Since both modes use the OSPI peripheral in the background, what different initializations does the RBL perform for each mode?

Note: In the AM263Px TRM, there is a section detailing the OSPI 8S boot mode and its flow, but there is no documentation explaining the xSPI boot flow.

0 Nilabh Anand 2 months ago in reply to Sanith goud Kothuri

TI__Mastermind 45084 points

Sanith goud Kothuri said:
f my SoC is running at 400 MHz and if I use XIP to execute instructions from OSPI flash running at 133 MHz, will there be any timing-related issues? Or to ensure smooth operation, do I need to apply any specific settings or configurations?

These are default SDK configuration, so no issue with this,

0 Nilabh Anand 2 months ago in reply to Sanith goud Kothuri

TI__Mastermind 45084 points

Sanith goud Kothuri said:
Another question: In boot modes, what is the exact difference between OSPI (8S) boot mode and xSPI (8D) boot mode? Since both modes use the OSPI peripheral in the background, what different initializations does the RBL perform for each mode?

Note: In the AM263Px TRM, there is a section detailing the OSPI 8S boot mode and its flow, but there is no documentation explaining the xSPI boot flow.

https://www.issi.com/WW/pdf/25LX-WX256-128.pdf

8s is mode where data is read from flash with each falling edge

8d , data is read on both falling and rising edge

...

0 Sanith goud Kothuri 2 months ago in reply to Nilabh Anand

Prodigy 85 points

We understand SDR and DDR modes, but we want a detailed explanation of the xSPI boot mode. Specifically, what does the RBL do when xSPI boot mode is selected? I'm asking this because there is no documentation about xSPI boot mode in the AM263Px TRM.

+1 Nilabh Anand 2 months ago in reply to Sanith goud Kothuri

TI__Mastermind 45084 points

Apart from the flash configuration, ROM does everything similar to 8S boot mode, Like 8S mode, 8D(xSPI) boot mode has different flash configuration.

I will take an action to get this updated in TRM.

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AM263P4-Q1: The xSPI (8D) SFDP Boot Loader operation and process is not documented anywhere in the TRM