Tool/software:
Hi TI team
Please find the image below. We are connecting a load to the microcontroller as shown below. Since we are allowing the load works at a known state, we are adding a pull-up resistor(10K) to the Gate of the FET.
The microcontroller is connected to the 3V3 core, and the Pull-up is connected to the 5V, since the I/O is capable of withstanding a 5V level.
When input to the FET is low, the gate voltage is low.
During input to the FET is high, what will be the amplitude level of the voltage that the gate receives(5V/3V3)?. Kindly clarify.
Regards,
Murugavel.S
