AM2431: Is it possible to run a program directly from external NOR flash memory without using internal SRAM?

Q1.

I think you probably need Execute-In-Place (XIP) technology for at least some of your slower code:

(+) [FAQ] OSPI FAQ for Sitara/Jacinto devices - Processors forum - Processors - TI E2E support forums

AM243x MCU+ SDK: Enabling XIP or eXecute In Place

Hello Ito,

K.Z said:

・Instead of moving the program from Nor Flash to internal SRAM and executing it,
is it possible to operate directly from external Nor Flash without using internal SRAM?

The above attached example works when customer wants to run the code directly from the OSPI .

While XIP (execute In Place) is technically possible from OSPI, it has significant performance limitations due to the slower access time for the flash as compared to DDR.

TI recommends copying the application from NOR Flash to either internal MSRAM or DDR memory and executing from there to achieve reliable performance. 

K.Z said:

・If the above is not possible and a program capacity of 2MB or more is required,
is the only option to move the Nor Flash program to DDR4 and connect it?
The program capacity is expected to be around 3MB, but I do not want to use DDR.
Please advise on a method to execute a 3MB program without using DDR.

For a code size around 3MB, and if DDR is not preferred, there are very limited options.

Internal MSRAM in AM243X is only around 2MB, and cannot hold a 3MB application.
So, possible alternatives include:
• XIP from OSPI NOR Flash: As mentioned earlier, you may consider using XIP mode from OSPI Flash, but this comes with performance penalties and is only feasible for non-time-critical parts of the code .

K.Z said:

・When the main power is turned off, I want to ensure that the contents of SRAM are not erased by enabling internal SRAM to operate using a sub-battery.
Is it possible to operate SRAM using a separate power source?
Also, what is the current consumption in that case?

The internal SRAM on AM243X cannot retain its content once the main power is off.

Currently, SOC does not support a dedicated SRAM retention mode with a sub-battery like in traditional RTC-retained SRAM or battery-backed SRAM.

Regards,

Anil.

Hi Anil,

Thank you for your reply.

Swargam Anil said:

• XIP from OSPI NOR Flash: As mentioned earlier, you may consider using XIP mode from OSPI Flash, but this comes with performance penalties and is only feasible for non-time-critical parts of the code .

Is it possible to deploy and execute critical some code in internal SRAM?
Non-critical code is executed from Flash.

We are also considering the Renesas R5F572NNDDFC#30. This device has 4 MB of internal flash memory, so it can store programs.
Which device has faster program execution speed? We plan to operate the R5F572NNDDFC#30 at around 120 MHz.

Best Regards,

Ito

Hello Ito,

The R5F runs at 800MHz on the AM243X.

I can say that the R5F core runs at 800MHz and the above MC runs at 120MHz and the speed execution of AM243X device is better compared to the above devices.

Please look at the benchmark details for AM64x/AM243X devices in the link below.

https://www.ti.com/lit/an/spracv1b/spracv1b.pdf?ts=1752211605929&ref_url=https%253A%252F%252Fwww.google.com%252F

K.Z said:

Is it possible to deploy and execute critical some code in internal SRAM?
Non-critical code is executed from Flash.

As per the SOC, this is possible, and you can run some code from the MSRAM and some code from the XIP.

So, you need to configure the Linker cmd file according to the above use case .

Please do the test on your side and let me know the test results.

Regards,

Anil.

Hi Anil,

Thank you for your reply.

Swargam Anil said:

I can say that the R5F core runs at 800MHz and the above MC runs at 120MHz and the speed execution of AM243X device is better compared to the above devices.

Is it faster than R5F572NNDDFC even when using XIP?
I understand that it will be faster if MSRAM is used.

Best Regards,

Ito