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MSPM0G3519: MCAN maximum RX FIFO size

Mesut KILIÇ
Prodigy 150 points
Part Number: MSPM0G3519

Tool/software:

Hello,

I am working on MCAN. I want to learn maximum rx fifo size. 

I only need 1 tx buffer. No need for tx fifo. I am only using rx fifo 0, no need for rx fifo 1. Also I don't use ID filters.

Rx fifo element size is 8 byte.

What can be the maximum rx fifo 0 size on this case?

Thanks

  • 0
    TI__Intellectual 2570 points

    Hi,

    The Rx FIFO can store up to 64 received messages. Please see the TRM for more information about this :) 

    -Matthew

  • 0 in reply to Matthew Komitsky
    Prodigy 150 points

    Hi,

    In DS section  8.27 CAN-FD "Dedicated 1kB message SRAM with ECC" Is that SRAM shared both CANFD0 and CANFD1?

    In TRM section 21.1.1 MCAN Features

    "Two configurable receive FIFOs, up to 14 elements each with 1kB message RAM"

    However in section  21.4.19.1 Message RAM Configuration at  Table 21-9. Message Transmission configurations

    if I use 8 byte frame size, maximum element size is 64. 

    If I set rx fifo size to 64, I will use all of the 1kB message SRAM. In that 1kB is that included rx fifo, tx buffer, tx event buffer and id filters?

    In my case I will use 1 tx fifo, no id filter, no tx event and 63 rx fifo. I will use only CANFD0. Is that calculation correct?

    Thanks

  • 0 in reply to Mesut KILIÇ
    TI__Intellectual 2570 points

    Hi,

    Each CAN instance has it's own message RAM.

    Take a look at the following graphic from the TRM that explains the element structure.

    -Matthew