AM2632: CPSW3G configuration and ethernet packet transmission issue

Shitanshu Desai

Part Number: AM2632

Tool/software:

I have AM263x launchpad and I am trying to configure the CPSW switch for AM2632 microcontroller.

I am using baremetal code to setup the clock and configure the CPSW switch. But, I am not able to transmit the ethernet packet.

Please check the following setup,

1. Port mode is selected as RGMII for MAC Port 1 and 2 through MSS_CTRL_CPSW_CONTROL register

2. 50 MHz clock enabled without changing default clock division value through MSS_RCM_MSS_MII100_CLK_GATE register for using MAC Port 1 and 2 in 100 Mbps mode

3. Enabled sub-blocks: CPSW NC, CPPI Port 0, MAC Port 1, MAC Port 2, CPDMA, ALE

4. Disabled sub-blocks: CPTS

5. Configured the buffer descriptor for transmit packet (Set flags: SOP,EOP, Owner; Cleared flags: EOQ)

6. Set transmit header descriptor pointer with buffer descriptor address through CPSW_NC_CPDMA_SRAM_TH0_HDP_REG register (My current understanding is, Thost registers are for transmit and Fhost registers are got receive transaction)

Please let me know if I am missing anything in my configuration. Also, if there is any PPT/document/addendum available which explains CPSW3G and the interaction between the sub-blocks with more details then please share that document as well.

Thank you,

Shitanshu Desai

1 month ago

0 Benjamin Collier 1 month ago

TI__Mastermind 36506 points

Hi,

Our expert on this topic is out until next week, I apologize for the delay in our response.

Best Regards,

Ben Collier

0 Shaunak Deshpande 1 month ago

TI__Genius 16282 points

Hi Shitanshu,

1. Are you using the example.syscfg to configure CPSW? If yes, can you please share the example.syscfg file? If no, can you please share the manual configuration code that you have written? (I'd recommend using Syscfg approach to avoid missing configs)

2. Can you please share what sample SDK application you are referring?

Please let me know if you can access this: https://texasinstruments.seismic.com/app#/contentmanager/detail/1/868e6789-5190-4f61-a874-65cf849821a5/info/LIST/title

Also, you can refer:

https://dev.ti.com/tirex/explore/content/am26x_academy_10_00_00_00/_build_am26x_academy_10_00_00_00/source/peripherals/general_networking/cpsw.html

https://dev.ti.com/tirex/explore/content/am26x_academy_10_00_00_00/_build_am26x_academy_10_00_00_00/source/debug_guides/ethernet_debug_guide.html

Regards,
Shaunak

0 Shitanshu Desai 1 month ago in reply to Shaunak Deshpande

Prodigy 50 points

Hi Shaunak,

I am not using example.syscfg. I am able to use transmit CPDMA interface. I configured the OCRAM address range to be non-cached.
Now, I am facing issue with the receive CPDMA interface.

In a ALE loop back test, the transmit buffer descriptor 'ownership' flag is resetting but the receive descriptor 'ownership' flag persists upon writing the descriptor address to Head Descriptor Pointer.

Also, how to arrange MAC packet frame fields in buffer data ?(DA, SA, Length, Data, CRC)

I am not able to access https://texasinstruments.seismic.com/app#/contentmanager/detail/1/868e6789-5190-4f61-a874-65cf849821a5/info/LIST/title link. It is asking for login credentials. I tried login credentials of this account but it did not work.

Thank you,
Shitanshu Desai

0 Shaunak Deshpande 1 month ago in reply to Shitanshu Desai

TI__Genius 16282 points

Hi Shitanshu,

It would be difficult to find the issue without having a complete look at the implementation. Generally I would recommend having syscfg do the auto-generation for the code.

Shitanshu Desai said:
Also, how to arrange MAC packet frame fields in buffer data ?(DA, SA, Length, Data, CRC)

This is with respect to the CPDMA buffers?

Regards,
Shaunak

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AM2632: CPSW3G configuration and ethernet packet transmission issue