Test 1:
To insert a single bit error and expecting an interrupt.
The below is the test sequence followed:
- Disable ECC in CPU by using the code given by the TI
- Disable ECC in EVEN RAM WRAPPER (0xFFFF F800) and enable ‘ECC WR EN’. Modifying from ‘0x0000 000A’ to ‘0x0000 0105’.
- Modify the RAM ECC DATA to ‘0x6E6E 6E6E’ from ‘0x0C0C 0C0C’. Note modified 64bit data.
- Enable ECC in RAM WRAPPER (0xFFFF F800) and disable ‘ECC WR EN’. Modifying from ‘0x0000 0105’ to ‘0x0000 000A’.
- Enable ECC in CPU by using the code given by TI. The below are the observations observed while executing this step.
- After the step ‘MCR P15, #0, R4, C1, C0, #1’ observed that the RAM DATA and the RAM ECC are modified as ‘0xADOB ADOB 0x0000 0001’ and ‘0xADOB ADOB 0x6E6E 6E6F’ respectively.
- The next step is ‘ISB’, after this step the RAM DATA modified as ‘0x0000 0000 0x0000 0001’. But the ECC DATA is still wrong.
Note: Move to step 7 to avoid the DATA ABORT.
6. Read ECC and observed DATA ABORT.
7. Disable ECC in CPU by using the code given by the TI. The below are the observations observed while executing this step.
a. After the step ‘MCR P15, #0, R4, C1, C0, #1’ observed that the ECC modified to the correct value as ‘0x6E6E 6E6E 0x6E6E 6E6E’
8. Disable ECC in ODDRAM WRAPPER (0xFFFF F900) and enable ‘ECC WR EN’. Modifying from ‘0x0000 000A’ to ‘0x0000 0105’.
9. Repeat the steps 3 to 6 and observed the same behavior.
If tries to read the ECC then observing the DATA ABORT. If not read the ECC observed that the ESM handler is taking care of the single bit error.
Test 2:
I created a pre-defined ECC table by using walking 1’s on a particular RAM location and noted the corresponding ECC. During normal operation, I am trying to change a RAM location with walking 1’s and expecting the corresponding ECC to be calculated and comparing the calculated ECC with the predefined table.
Observations:
- Modified the RAM Location from ‘0x0000 0000 to 0x0000 0001’. Then the corresponding ECC modified as ‘0xADOB ADOB 0x6E6E 6E6F’.
- Then if tries to read the ECC location then observed the DATA ABORT.
- When the software hits the Boot DABT handler then the corresponding ECC modified as ‘0x6E6E 6E6E 0x6E6E 6E6E’.
The below is the code snippet followed to Enable and Disable the ECC respectively.
Enable ECC
; Enable Events on Event Bus
MRC P15, #0, R4, C9, C12, #0
ORR R4, R4, #0x00000010
MCR P15, #0, R4, C9, C12, #0
; Enable ECC for Memories
MRC P15, #0, R4, C1, C0, #1
ORR R4, R4, #0x1 <<26
DMB
MCR P15, #0, R4, C1, C0, #1 “Step 5.a”
ISB “Step 5.b”
MRC P15, #0, R4, C1, C0, #1
ORR R4, R4, #0x1 <<27
DMB
MCR P15, #0, R4, C1, C0, #1
ISB
BX LR
Disable ECC
; Disbale ECC for Memories
MRC P15, #0, R4, C1, C0, #1
MVN R5, #0x1 <<26
AND R4, R4, R5
MVN R5, #0x1 <<27
AND R4, R4, R5
DMB
MCR P15, #0, R4, C1, C0, #1 “Step 7.a”
ISB
MRC P15, #0, R4, C1, C0, #1
DMB
MCR P15, #0, R4, C1, C0, #1
ISB
; Disable Events on Event bus
MRC P15, #0, R4, C9, C12, #0
MVN R5, #0x00000010
AND R4, R4, R5
DMB
MCR P15, #0, R4, C9, C12, #0
ISB
BX LR
