MCU-PLUS-SDK-AM263PX: Enabling ECC and PBIST in SBL

Hi Deviprasad,

Thanks for contacting TI.

I am working on your issue now, i will try to post my updates on this as soon as possible.

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Thanks & regards,
Jagadish.

Deviprasad Nagadavalli said:

As per Section 5.9.2 Logger, the RBL uses the logger module for debug information. How can the detected failures be transmitted to the SBL so that it is aware of a failure scenario in the RBL?

If there are any errors in the RBL, the SBL would not come up at all. Hence, we have this logger memory to understand the cause of error in ROM.

Deviprasad Nagadavalli said:

As per Section 5.9.2 Logger, any failures detected by the R5 or HSM during boot can lead to an SoC warm reset after 180 seconds. Can this timeout be reduced based on our requirements?

No, this timeout is fixed to 180 seconds. This is an HSM Watchdog which would be disabled once the customer HSMRT is loaded and both the MSS ROM and HSM ROM are eclipsed. So in SBL, you can configure the R5 Watchdogs as per your requirements.

Deviprasad Nagadavalli said:

In the logger module, what types of failures can the RBL log?

It would mostly be failures in either certificate validation or SBL integrity check failures or PBIST failure on the MSS ROM side which could be seen using this logger info.

Deviprasad Nagadavalli said:

Need some good understanding on PBIST.

1. Is PBIST configured and enabled only by the ROM bootloader?
2. What is the behavior/action of RBL If PBIST finds failure in TCMB or TCMA or L2 memory? Will it get stuck in RBL in such failure scenario?
3. If SBL can initiate PBIST, how can it test TCMA and L2 memory regions without causing any memory corruption?

The attached document could give you a clear understanding on the regions the PBIST is done on ROM and SBL. 

The questions 1,2 and 3 will be answered by jagadish gundavarapu 

Thanks and Regards,

Nikhil Dasan

1. As per your reply failures like certificate validation or SBL integrity check failures or PBIST failure on the MSS ROM are available in logger. Apart from these failures RBL may be performing other tests as well. Kindly share the complete list of failures that can be detected by the RBL.
2. Can our customized SBL be used to test TCMA and TCMB memory without using PBIST module?
3. Please explain in detail how to take care of the below scenario under section 13.6.6.3. 
   R5SS VIM Memories – Since ISR is stored in VIM memories, if VIM memories are to be tested, polling on
   interrupt line should be done and not ISR execution.
   

Hi jagadish gundavarapu 

Could you please share the details for the first three questions I posted earlier?

1. Will the ECC bits are enabled by RBL development boot mode(debug)?
2. What is the behavior when ECC fails when RBL is running?
3. During a data abort exception, how can one differentiate between a double-bit error and an inject-only mode trigger?

Thanks,

Deviprasad N.

Hi Nikhil Dasan 

Could you please send me addition details as per recent questions related to PBIST?

Thanks,

Deviprasad N.

Hi Deviprasad,

Apologies for the delayed response!

For OCRAM the ECC will always be in enabled mode only. For external flash need to enable it manually.

You can refer below link to understand on how to enable ECC for OSPI:

AM263Px MCU+ SDK: Enabling safety on external flash

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Thanks & regards,
Jagadish.