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MSPM0G3506: The amplifier configurations issue for MSPM0G3506

Zhang Liang
Genius 4125 points
Part Number: MSPM0G3506

Tool/software:

Hi,

1. Can you help to advise what circumstances will the comparator COMP0 of MSPM0G3506 be set to amplifier mode, and its output will change year-on-year based on the input (analog output), 
     rather than flipping to high or low level after comparison?
2. We are now experiencing a strange phenomenon: in the past, the output of the comparator was connected to the RxD of the CPU's UART,
    and the output of the comparator was high and low levels; But now we have cancelled the UART function and used RxD as the GPIO input port,
3. while the comparator settings have not been changed. However, the comparator has become similar to an operational amplifier,
    and its compared output has become an analog signal that changes synchronously with the comparator input.
4. When adjusting the input, it can be seen that the output of the comparator also changes accordingly. Previously, the output was high and low levels, and when adjusted to a certain 2.5V, it suddenly flipped.
  
    Previously, the output was digital, but now it has become analog output, the settings of the comparator have not been changed in the software
  • 0
    TI__Mastermind 18327 points
    Zhang Liang said:
    1. Can you help to advise what circumstances will the comparator COMP0 of MSPM0G3506 be set to amplifier mode, and its output will change year-on-year based on the input (analog output), 
         rather than flipping to high or low level after comparison?

    COMP is not a amplifier, please try the same settings on other MSPM0 to see if the phenomenon is the same.

    Zhang Liang said:
    4. When adjusting the input, it can be seen that the output of the comparator also changes accordingly. Previously, the output was high and low levels, and when adjusted to a certain 2.5V, it suddenly flipped.
      
        Previously, the output was digital, but now it has become analog output, the settings of the comparator have not been changed in the software

    Try to re-program device, and try again.

    Or run factory reset: For CCS unlock MSPM0, please refer to https://www.ti.com/lit/pdf/slaaed1 7.1.4 Unlock Through CCS

    If you remove the chips from PCB, you can try to test the resistance between IO and GND (power off), compare the value with normal chips(without soldering on PCB)

  • 0 in reply to Helic Chi
    Genius 4125 points

    Hi Helic,

    Thanks for you kindly support, now we have below issue:

    Using 4-wire mode (chip select CS0), with a data frame size of 16 bits, and allowing the PACKEN function, two16-bit values are packed into a 32-bit value.

    However, actual measurements show that CS0 is not valid throughout the entire 32-bit period, but rather experiences a high-level failure of approximately
    0.5us between the first 16 bits and the last 16 bits.
    In other words, it performs two 16-bit transmissions instead of one 32-bit transmission.

    We also tried sending 4 8-bit bytes through TX FIFO, but the actual measurement showed that CS0 was only valid between each 8-bit byte, and CS0 would
    briefly become invalid between each 8-bit byte.

    However, the currently connected peripherals of SPI use this 32-bit unit as a communication frame, during which CS must remain valid at all times.

    This is our question: Is it possible to set CS0 as a low-level chip select signal for the entire 32-bit system?

    If the answer is no, then we can only choose the 3-wire mode and control CS0 through software.
  • 0 in reply to Zhang Liang
    TI__Mastermind 18327 points
    Zhang Liang said:
    Using 4-wire mode (chip select CS0), with a data frame size of 16 bits, and allowing the PACKEN function, two16-bit values are packed into a 32-bit value.

    This PACKEN is CPU interface, not SPI 32bit output.

    Zhang Liang said:
    However, actual measurements show that CS0 is not valid throughout the entire 32-bit period, but rather experiences a high-level failure of approximately
    0.5us between the first 16 bits and the last 16 bits.
    In other words, it performs two 16-bit transmissions instead of one 32-bit transmission.

    In default clock config, SPI SCK is not send data continuously, that's why CS has a high pulse.

    SPH = 1 will keep CS low and CLK continuous.