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MSPM0G1507: 12Bits DAC Resolution

George Zhang
Prodigy 70 points
Part Number: MSPM0G1507

Tool/software:

Hello TI Experts,

According to Table 7.16.4, the DAC has an offset error of ±20 mV without calibration or ±2 mV with calibration. Is this offset considered part-to-part variation, or can it also drift on the same device under different temperatures?

I'm trying to estimate the worst-case output error. Currently, I sum the INL, gain error (Eg), and offset error (Eo). For example, using the internal Vref and an output range from 0.3 V to 1.4 V:

Offset error (Eo): 20 mV (assuming no calibration)

INL: (1.1 V / 4096) × 2 ≈ 0.57 mV

Gain error (Eg): 1% of 1.1 V ≈ 11 mV

This gives a total worst-case error of approximately 31 mV.

Is this correct?

Thank you,

George

  • +1
    TI__Prodigy 180 points

    Hi George,

    The offset error spec is across all the devices and all the temperatures.

    To answer your second question:

    • The Internal Vref should be 1.4V / 2.5V in your case will be 1.4V
    • According to the data sheet:
      • INL: ± 4 LSB Max 
      • Gain Error(Eg) = 2% = ± 82 LSB
      • Offset Error(Eo) = ± 20 mV = ± 58 LSB
    • Total unadjusted error uncalibrated equation

    TUE = 100.51 LSB

    I hope this answers your question.

    Best regards,

    Bill

  • 0 in reply to Bill Tang
    Prodigy 70 points

    Hello Bill,

    Thanks for your quick response. Is there a way to estimate the worst-case output error for a single device across temperature? We're less concerned about part-to-part variation, our main concern is potential drift over time or temperature for a given unit.

    Thank you,

    George

  • 0 in reply to George Zhang
    TI__Prodigy 180 points

    Hello George,

    The data sheet spec it is across temperature. The calculation I provide above is using the worst-case output error across temperature. Please let me know if that helps.

    Best regards,

    Bill